Patents by Inventor Giulia Colonna

Giulia Colonna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Synthesis driven for minimum leakage with new standard cells
    Patent number: 12184277
    Abstract: According to an embodiment, an integrated circuit includes a complementary metal-oxide-semiconductor (CMOS) logic gate, a series p-channel transistor, and a shunt n-channel transistor. The CMOS logic gate includes a first p-channel transistor and a first n-channel transistor. The first p-channel transistor and the series p-channel transistor are configurable to be body biased. The series p-channel transistor is coupled between an output terminal of the CMOS logic gate and the first p-channel transistor. The shunt n-channel transistor is coupled between the output terminal of the CMOS logic gate and the reference ground. A gate terminal of the series p-channel transistor is coupled to a gate terminal of the shunt n-channel transistor and configured to receive a sleep signal during a low-power operating mode of the CMOS logic gate.
    Type: Grant
    Filed: April 27, 2023
    Date of Patent: December 31, 2024
    Assignee: STMicroelectronics International N.V.
    Inventors: Giulia Colonna, Enea Dimroci
  • SYNTHESIS DRIVEN FOR MINIMUM LEAKAGE WITH NEW STANDARD CELLS
    Publication number: 20240364336
    Abstract: According to an embodiment, an integrated circuit includes a complementary metal-oxide-semiconductor (CMOS) logic gate, a series p-channel transistor, and a shunt n-channel transistor. The CMOS logic gate includes a first p-channel transistor and a first n-channel transistor. The first p-channel transistor and the series p-channel transistor are configurable to be body biased. The series p-channel transistor is coupled between an output terminal of the CMOS logic gate and the first p-channel transistor. The shunt n-channel transistor is coupled between the output terminal of the CMOS logic gate and the reference ground. A gate terminal of the series p-channel transistor is coupled to a gate terminal of the shunt n-channel transistor and configured to receive a sleep signal during a low-power operating mode of the CMOS logic gate.
    Type: Application
    Filed: April 27, 2023
    Publication date: October 31, 2024
    Inventors: Giulia Colonna, Enea Dimroci