Patents by Inventor Giuliano Gennaro Imondi

Giuliano Gennaro Imondi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory area protection system and methods
    Patent number: 9406388
    Abstract: In one embodiment, a non-volatile memory device includes a plurality of protection bits denoting that an area of memory in the device must be protected from being erased or programmed. The memory device further includes a majority logic circuit for determining the logic state of the majority of the plurality of protection bits. Another embodiment includes a pattern generator for generating the logic levels to be stored in the plurality of protection bits.
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: August 2, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Luca De Santis, Maria Luisa Gallese, Giuliano Gennaro Imondi
  • Pipelined burst memory access
    Patent number: 7949844
    Abstract: A memory device for multichannel continuous or fixed burst mode operation includes multiple burst address counter circuits and associated control logic to minimize latency which would otherwise occur in multichannel operation.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: May 24, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Giuliano Gennaro Imondi, Maurizio Di Zenzo, Mario Antonio Fazio
  • Memory Area Protection System and Methods
    Publication number: 20100138623
    Abstract: In one embodiment, a non-volatile memory device includes a plurality of protection bits denoting that an area of memory in the device must be protected from being erased or programmed. The memory device further includes a majority logic circuit for determining the logic state of the majority of the plurality of protection bits. Another embodiment includes a pattern generator for generating the logic levels to be stored in the plurality of protection bits.
    Type: Application
    Filed: May 10, 2007
    Publication date: June 3, 2010
    Applicant: Micron Technology, Inc
    Inventors: Luca De Santis, Maria Luisa Gallese, Giuliano Gennaro Imondi
  • Background block erase check for flash memories
    Patent number: 7565587
    Abstract: Memory devices and methods of operating memory devices provide for using differing potentials during erase verify operations facilitate normal erase operations and subsequent erase check operations. Such apparatus and methods facilitate subsequent checks for data gain of erased memory cells using abbreviated procedures compared to normal erase operations.
    Type: Grant
    Filed: September 12, 2006
    Date of Patent: July 21, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Giuliano Gennaro Imondi, Giovanni Naso
  • PIPELINED BURST MEMORY ACCESS
    Publication number: 20080195795
    Abstract: A memory device for multichannel continuous or fixed burst mode operation includes multiple burst address counter circuits and associated control logic to minimize latency which would otherwise occur in multichannel operation.
    Type: Application
    Filed: April 22, 2008
    Publication date: August 14, 2008
    Inventors: Giuliano Gennaro Imondi, Maurizio Di Zenzo, Mario Antonio Fazio
  • Pipelined burst memory access
    Patent number: 7363452
    Abstract: A memory device for multichannel continuous or fixed burst mode operation includes multiple burst address counter circuits and associated control logic to minimize latency which would otherwise occur in multichannel operation.
    Type: Grant
    Filed: January 31, 2006
    Date of Patent: April 22, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Giuliano Gennaro Imondi, Maurizio Di Zenzo, Mario Antonio Fazio
  • No-precharge FAMOS cell and latch circuit in a memory device
    Patent number: 7263022
    Abstract: The fuse and latch circuit has a Floating gate Avalanche injection Metal Oxide Semiconductor (FAMOS) transistor (fuse) that is coupled to a read circuit. The read circuit includes circuitry that reduces the drive strength of the fuse. A transmission gate couples the read circuit to the latch circuit. The transmission gate isolates the fuse from the latch. When a reset condition occurs, the data that was in latch circuit remains after the reset condition is complete.
    Type: Grant
    Filed: June 22, 2006
    Date of Patent: August 28, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Giuliano Gennaro Imondi
  • Dual bus memory burst architecture
    Patent number: 7164607
    Abstract: Methods and apparatus for a memory device including a burst architecture employ a double bus architecture that is multiplexed onto an output bus. The resulting architecture effectively facilitates doubling throughput without increasing memory device latency.
    Type: Grant
    Filed: June 1, 2005
    Date of Patent: January 16, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Girolamo Gallo, Giuliano Gennaro Imondi, Giovanni Naso, Tommaso Vali
  • No-precharge FAMOS cell and latch circuit in a memory device
    Patent number: 7154800
    Abstract: The fuse and latch circuit has a Floating gate Avalanche injection Metal Oxide Semiconductor (FAMOS) transistor (fuse) that is coupled to a read circuit. The read circuit includes circuitry that reduces the drive strength of the fuse. A transmission gate couples the read circuit to the latch circuit. The transmission gate isolates the fuse from the latch. When a reset condition occurs, the data that was in latch circuit remains after the reset condition is complete.
    Type: Grant
    Filed: August 4, 2005
    Date of Patent: December 26, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Giuliano Gennaro Imondi
  • Background block erase check for flash memories
    Patent number: 7117402
    Abstract: A flash memory erase check circuit is disclosed. One embodiment includes an on-chip circuit that quickly and reliably checks that the flash memory chip is actually erased even after data gain that has resulted, for example, from a long period of storage.
    Type: Grant
    Filed: November 1, 2002
    Date of Patent: October 3, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Maurizio Di Zenzo, Maria Luisa Gallese, Giuliano Gennaro Imondi, Giovanni Naso
  • Pipelined burst memory access
    Patent number: 7020737
    Abstract: A memory device for multichannel continuous or fixed burst mode operation includes multiple burst address counter circuits and associated control logic to minimize latency which would otherwise occur in multichannel operation.
    Type: Grant
    Filed: February 13, 2003
    Date of Patent: March 28, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Giuliano Gennaro Imondi, Maurizio Di Zenzo, Mario Antonio Fazio
  • No-precharge FAMOS cell and latch circuit in a memory device
    Patent number: 6967889
    Abstract: The fuse and latch circuit has a Floating gate Avalanche injection Metal Oxide Semiconductor (FAMOS) transistor (fuse) that is coupled to a read circuit. The read circuit includes circuitry that reduces the drive strength of the fuse. A transmission gate couples the read circuit to the latch circuit. The transmission gate isolates the fuse from the latch. When a reset condition occurs, the data that was in latch circuit remains after the reset condition is complete.
    Type: Grant
    Filed: December 2, 2003
    Date of Patent: November 22, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Giuliano Gennaro Imondi
  • Dual bus memory burst architecture
    Patent number: 6917545
    Abstract: A method and apparatus for a memory device including a burst architecture employs a double bus architecture that is multiplexed onto an output bus at clock rate that is doubled. The resulting architecture effectively doubles throughput without increasing memory device latency.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: July 12, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Girolamo Gallo, Giuliano Gennaro Imondi, Giovanni Naso, Tommaso Vali
  • Dual bus memory burst architecture
    Publication number: 20040071037
    Abstract: A method and apparatus for a memory device including a burst architecture employs a double bus architecture that is multiplexed onto an output bus at clock rate that is doubled. The invention effectively doubles throughput without increasing memory device latency.
    Type: Application
    Filed: February 14, 2003
    Publication date: April 15, 2004
    Inventors: Girolamo Gallo, Giuliano Gennaro Imondi, Giovanni Naso, Tommaso Vali
  • Pipelined burst memory access
    Publication number: 20030214854
    Abstract: A memory device for multichannel continuous or fixed burst mode operation includes multiple burst address counter circuits and associated control logic to minimize latency which would otherwise occur in multichannel operation.
    Type: Application
    Filed: February 13, 2003
    Publication date: November 20, 2003
    Inventors: Giuliano Gennaro Imondi, Maurizio Di Zenzo, Mario Antonio Fazio
  • Background block erase check for flash memories
    Publication number: 20030101390
    Abstract: A flash memory erase check circuit is disclosed. One embodiment includes an on-chip circuit that quickly and reliably checks that the flash memory chip is actually erased even after data gain that has resulted, for example, from a long period of storage.
    Type: Application
    Filed: November 1, 2002
    Publication date: May 29, 2003
    Inventors: Maurizio Di Zenzo, Maria Luisa Gallese, Giuliano Gennaro Imondi, Giovanni Naso