Abstract: Ramp comparator pulse generators having temperature and voltage compensation are adapted for use in integrated circuit devices such as memory devices. Such pulse generators include a ramp signal generator, a threshold signal generator, and a comparator providing an output signal in response to a difference between the potential level of the threshold signal and the potential level of the ramp signal. The pulse generators described herein utilize an adaptive threshold signal generator configured as a voltage divider and having resistive components having differing effective temperature coefficients of resistivity. The adaptive threshold signal generator has an upper resistive component and a lower resistive component coupled in series between a high potential node and a low potential node. The lower resistive component has an effective temperature coefficient of resistivity that is less than an effective temperature coefficient of resistivity of the upper resistive component.

Abstract: Methods of sensing the programmed state of a floating-gate memory cell utilize a reference current applied to an input node of a sensing device during sensing, thus compensating for residual current and improving immunity to erroneous indications of an erased state.

Abstract: Ramp comparator pulse generators having temperature and voltage compensation are adapted for use in integrated circuit devices such as memory devices. Such pulse generators include a ramp signal generator, a threshold signal generator, and a comparator providing an output signal in response to a difference between the potential level of the threshold signal and the potential level of the ramp signal. The pulse generators described herein utilize an adaptive threshold signal generator configured as a voltage divider and having resistive components having differing effective temperature coefficients of resistivity. The adaptive threshold signal generator has an upper resistive component and a lower resistive component coupled in series between a high potential node and a low potential node. The lower resistive component has an effective temperature coefficient of resistivity that is less than an effective temperature coefficient of resistivity of the upper resistive component.

Abstract: Methods of sensing the programmed state of a floating-gate memory cell utilize a reference current applied to an input node of a sensing device during sensing, thus compensating for residual current and improving immunity to erroneous indications of an erased state.

Abstract: Ramp comparator pulse generators having temperature and voltage compensation are adapted for use in integrated circuit devices such as memory devices. Such pulse generators include a ramp signal generator, a threshold signal generator, and a comparator providing an output signal in response to a difference between the potential level of the threshold signal and the potential level of the ramp signal. The pulse generators described herein utilize an adaptive threshold signal generator configured as a voltage divider and having resistive components having differing effective temperature coefficients of resistivity. The adaptive threshold signal generator has an upper resistive component and a lower resistive component coupled in series between a high potential node and a low potential node. The lower resistive component has an effective temperature coefficient of resistivity that is less than an effective temperature coefficient of resistivity of the upper resistive component.

Abstract: Single-ended sensing devices for sensing a programmed state of a floating-gate memory cell are adapted for use in low-voltage memory devices. The sensing device has an input node selectively coupled to the memory cell. The sensing device includes a precharging path for applying a precharge potential to the input node of the sensing device for precharging bit lines prior to sensing the programmed state of the memory cell, and a reference current path for applying a reference current to the input node of the sensing device. The sensing device still further includes a sense inverter having an input coupled to the input node of the sensing device and an output for providing an output signal indicative of the programmed state of the memory cell. The reference current is applied to the input node of the sensing device during sensing of the programmed state of the memory cell.

Abstract: Ramp comparator pulse generators having temperature and voltage compensation are adapted for use in integrated circuit devices such as memory devices. Such pulse generators include a ramp signal generator, a threshold signal generator, and a comparator providing an output signal in response to a difference between the potential level of the threshold signal and the potential level of the ramp signal. The pulse generators described herein utilize an adaptive threshold signal generator configured as a voltage divider and having resistive components having differing effective temperature coefficients of resistivity. The adaptive threshold signal generator has an upper resistive component and a lower resistive component coupled in series between a high potential node and a low potential node. The lower resistive component has an effective temperature coefficient of resistivity that is less than an effective temperature coefficient of resistivity of the upper resistive component.

Abstract: Column select circuits having improved immunity to supply potential noise during sensing of the programmed state of a target memory cell are suited for use in low-voltage memory devices. Such column select circuits contain driver circuits having a filtered path and an unfiltered path for applying a supply potential to a gate of a pass transistor. The unfiltered path is utilized during a first sensing phase, such as during decoding or precharging of the bit lines, when transition speed of the pass transistors is desired. The filtered path is utilized at least during a second sensing phase while the sensing device is detecting the programmed state of the target memory cell. By reducing the noise of the supply potential using the filtered path, margins are improved on the sensing device and the sensing device is thus capable of operating at lower supply potentials.

Abstract: A semiconductor device comprising an integrated circuit and an information unit, said unit being electrically separate from said integrated circuit; an integrated antenna electrically connected with said unit; and an electronic data bank integral with said unit. A method of fabricating an information unit into an integrated circuit chip comprising forming an integrated circuit into a semiconductor substrate using a plurality of process steps; concurrently forming an information unit using a selection of said process steps so that said unit becomes integrated into said chip but remains electrically separate from said integrated circuit; concurrently forming an antenna using a selection of said process steps so that said antenna becomes integrated into said chip and electrically connected to said information unit; providing a data bank within said information unit; and encoding electronic data permanently into said data bank.

Abstract: Ramp comparator pulse generators having temperature and voltage compensation are adapted for use in integrated circuit devices such as memory devices. Such pulse generators include a ramp signal generator, a threshold signal generator, and a comparator providing an output signal in response to a difference between the potential level of the threshold signal and the potential level of the ramp signal. The pulse generators described herein utilize an adaptive threshold signal generator configured as a voltage divider and having resistive components having differing effective temperature coefficients of resistivity. The adaptive threshold signal generator has an upper resistive component and a lower resistive component coupled in series between a high potential node and a low potential node. The lower resistive component has an effective temperature coefficient of resistivity that is less than an effective temperature coefficient of resistivity of the upper resistive component.

Abstract: Single-ended sensing devices for sensing a programmed state of a floating-gate memory cell are adapted for use in low-voltage memory devices. The sensing device has an input node selectively coupled to the memory cell. The sensing device includes a precharging path for applying a precharge potential to the input node of the sensing device for precharging bit lines prior to sensing the programmed state of the memory cell, and a reference current path for applying a reference current to the input node of the sensing device. The sensing device still further includes a sense inverter having an input coupled to the input node of the sensing device and an output for providing an output signal indicative of the programmed state of the memory cell. The reference current is applied to the input node of the sensing device during sensing of the programmed state of the memory cell.

Abstract: Column select circuits having improved immunity to supply potential noise during sensing of the programmed state of a target memory cell are suited for use in low-voltage memory devices. Such column select circuits contain driver circuits having a filtered path and an unfiltered path for applying a supply potential to a gate of a pass transistor. The unfiltered path is utilized during a first sensing phase, such as during decoding or precharging of the bit lines, when transition speed of the pass transistors is desired. The filtered path is utilized at least during a second sensing phase while the sensing device is detecting the programmed state of the target memory cell. By reducing the noise of the supply potential using the filtered path, margins are improved on the sensing device and the sensing device is thus capable of operating at lower supply potentials.

Abstract: A semiconductor device comprising an integrated circuit and an information unit, said unit being electrically separate from said integrated circuit; an integrated antenna electrically connected with said unit; and an electronic data bank integral with said unit. A method of fabricating an information unit into an integrated circuit chip comprising forming an integrated circuit into a semiconductor substrate using a plurality of process steps; concurrently forming an information unit using a selection of said process steps so that said unit becomes integrated into said chip but remains electrically separate from said integrated circuit; concurrently forming an antenna using a selection of said process steps so that said antenna becomes integrated into said chip and electrically connected to said information unit; providing a data bank within said information unit; and encoding electronic data permanently into said data bank.

Abstract: Segmentation of FLASH Memory arrays allows the global and local bit lines to be isolated, greatly reducing global bit line capacitance, reducing bit line stress, and eliminating boot block disturb effects. Reduction in bit line capacitance also results in fast access time greatly improving the ability to implement larger arrays without paying severe access time penalties.

Abstract: FLASH Memory sense amplifier reference circuit with weighted dummy loads is used to balance and bias the sense amplifier during erasing, programming, and verification such that the resulting robust stored logic states can meet more stringent pass-fail verify “1” or verify “0” tests. Programming in this manner guarantees logic states which meet full operating temperature and full power supply tolerances requirements.

Abstract: FLASH Memory hardware Block or sector Clear Operation using a single block or sector operation without using "byte-mode" processing is described. This hardware Block or sector Clear operation does not use avalanche injection, and has several distinct advantages, including programming simplicity, increased device reliability and yield. Use of the hardware block or sector clear operation described here results in increased programming speed, faster chip testing, and faster write/erase cycling compared to the normal operations of prior art.

Abstract: A low voltage flash EEPROM X-Cell includes an array of memory cell transistors (24) that constitute asymmetric floating gate memory cells wherein programming is achieved on only one side of the memory cells (24). The programming side of each of the memory cells (24) is connected to one of a plurality of Column Lines (28) at nodes (30). Each node (30) shares the programming side of two of the memory cells (24) and the non-programming side of two of the memory cells (24). The control gates of each of the memory cells (24) are connected to Word Lines (26) associated with rows of the array. To Flash Write all of the memory cells (24), the Column Lines (38) are connected to a negative medium voltage and the row lines (26) are connected to a positive medium voltage.