Patents by Inventor GIUSEPPE A. LAPIANA

GIUSEPPE A. LAPIANA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10205454
    Abstract: Apparatus for glitch-free switching between multiple asynchronous clock sources on an integrated circuit. Clock gaters provide a clock from a single source that can be turned on and off without causing partial pulses to be created. Control circuitry going to the individual clock gaters is synchronized to the destination clock domain and provides the ability to shut all clocks off for a period of time equal to the longest clock period. By combining the clocks with an OR gate and gating all clocks off before switching from one clock to another, a glitch-free train of clock pulses can be created from individual clock inputs. Since clock glitches can cause erratic behavior in integrated circuits, this invention allows one to switch between different, asynchronous clocks without causing erratic behavior.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: February 12, 2019
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventor: Giuseppe A. Lapiana
  • Publication number: 20180145689
    Abstract: Apparatus for glitch-free switching between multiple asynchronous clock sources on an integrated circuit. Clock gaters provide a clock from a single source that can be turned on and off without causing partial pulses to be created. Control circuitry going to the individual clock gaters is synchronized to the destination clock domain and provides the ability to shut all clocks off for a period of time equal to the longest clock period. By combining the clocks with an OR gate and gating all clocks off before switching from one clock to another, a glitch-free train of clock pulses can be created from individual clock inputs. Since clock glitches can cause erratic behavior in integrated circuits, this invention allows one to switch —between different, asynchronous clocks without causing erratic behavior.
    Type: Application
    Filed: November 22, 2016
    Publication date: May 24, 2018
    Inventor: GIUSEPPE A. LAPIANA