Patents by Inventor Giuseppe Alessio Maria D'Arrigo

Giuseppe Alessio Maria D'Arrigo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8890103
    Abstract: A semiconductive substrate that is suitable for realising electronic and/or optoelectronic devices that include at least one substrate, in particular of single crystal silicon, and an overlying layer of single crystal silicon. Advantageously, the semiconductive substrate comprises at least one functional coupling layer suitable for reducing the defects linked to the differences in the materials used. The functional coupling layer can comprise a corrugated portion made in the layer of single crystal silicon and suitable for reducing the defects linked to the differences in lattice constant of such materials used. Alternatively, the functional coupling layer can comprise a porous layer arranged between the substrate of single crystal silicon and the layer of single crystal silicon, and suitable for reducing the stress caused by the differences between the thermal expansion coefficients of the materials used. A manufacturing process of such a semiconductive substrate is also described.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: November 18, 2014
    Assignee: Consiglio Nazionale Delle Ricerche
    Inventors: Giuseppe Alessio Maria D'Arrigo, Francesco La Via
  • Publication number: 20120133027
    Abstract: A semiconductive substrate that is suitable for realising electronic and/or optoelectronic devices that include at least one substrate, in particular of single crystal silicon, and an overlying layer of single crystal silicon. Advantageously, the semiconductive substrate comprises at least one functional coupling layer suitable for reducing the defects linked to the differences in the materials used. The functional coupling layer can comprise a corrugated portion made in the layer of single crystal silicon and suitable for reducing the defects linked to the differences in lattice constant of such materials used. Alternatively, the functional coupling layer can comprise a porous layer arranged between the substrate of single crystal silicon and the layer of single crystal silicon, and suitable for reducing the stress caused by the differences between the thermal expansion coefficients of the materials used. A manufacturing process of such a semiconductive substrate is also described.
    Type: Application
    Filed: November 18, 2011
    Publication date: May 31, 2012
    Applicant: Consiglio Nazionale Delle Ricerche
    Inventors: Giuseppe Alessio Maria D'Arrigo, Francesco La Via
  • Publication number: 20100013057
    Abstract: A semiconductive substrate (1) is described that is suitable for realising electronic and/or optoelectronic devices of the type comprising at least one substrate (3), in particular of single crystal silicon, and an overlying layer of single crystal silicon (5). Advantageously, according to the invention, the semiconductive substrate (1) comprises at least one functional coupling layer (10) suitable for reducing the defects linked to the differences in the materials used. In particular, the functional coupling layer 10 comprises a corrugated portion (6) made in the layer of single crystal silicon (5) and suitable for reducing the defects linked to the differences in lattice constant of such materials used.
    Type: Application
    Filed: July 16, 2009
    Publication date: January 21, 2010
    Applicant: Consiglio Nazionale Delle Ricerche
    Inventors: Giuseppe Alessio Maria D'Arrigo, Francesco La Via