Abstract: A vertical-conduction MOSFET device, includes: a semiconductor body, having a front side and a back side and having a first conductivity; a trench-gate region; a body region, having the first conductivity; a source region, having a second conductivity; and a drain region, having the second conductivity. The source region, body region, and drain region are aligned with one another along a first direction and define a channel area, which, in a conduction state of the MOSFET device, hosts a conductive channel. The drain region borders on a portion of the semiconductor body having the first conductivity, thus forming a junction diode, which, in an inhibition state of the MOSFET device, is adapted to cause a leakage current to flow outside the channel area.

Abstract: A vertical-conduction MOSFET device, includes: a semiconductor body, having a front side and a back side and having a first conductivity; a trench-gate region; a body region, having the first conductivity; a source region, having a second conductivity; and a drain region, having the second conductivity. The source region, body region, and drain region are aligned with one another along a first direction and define a channel area, which, in a conduction state of the MOSFET device, hosts a conductive channel. The drain region borders on a portion of the semiconductor body having the first conductivity, thus forming a junction diode, which, in an inhibition state of the MOSFET device, is adapted to cause a leakage current to flow outside the channel area.

Abstract: A non-volatile memory device integrated on a semiconductor substrate of a first type of conductivity comprising a matrix of non-volatile memory cells organized in rows, called word lines, and columns, called bit lines, the device including a plurality of equidistantly spaced active areas with the non-volatile memory cells integrated therein, each non-volatile memory cell having a source region, a drain region and a floating gate electrode coupled to a control gate electrode, a group of the memory cells sharing a common source line of a second type of conductivity, an implanted region of said second type of conductivity inside at least one of the plurality of active areas in electric contact with the common source line, and at least one source contact aligned and in electric contact with the implanted region.

Abstract: A non-volatile memory device integrated on a semiconductor substrate of a first type of conductivity comprising a matrix of non-volatile memory cells organized in rows, called word lines, and columns, called bit lines, the device including a plurality of equidistantly spaced active areas with the non-volatile memory cells integrated therein, each non-volatile memory cell having a source region, a drain region and a floating gate electrode coupled to a control gate electrode, a group of the memory cells sharing a common source line of a second type of conductivity, an implanted region of said second type of conductivity inside at least one of the plurality of active areas in electric contact with the common source line, and at least one source contact aligned and in electric contact with the implanted region.