Abstract: An embodiment of a MOS device resistant to ionizing-radiation, has: a surface semiconductor layer with a first type of conductivity; a gate structure formed above the surface semiconductor layer, and constituted by a dielectric gate region and a gate-electrode region overlying the dielectric gate region; and body regions having a second type of conductivity, formed within the surface semiconductor layer, laterally and partially underneath the gate structure. In particular, the dielectric gate region is formed by a central region having a first thickness, and by side regions having a second thickness, smaller than the first thickness; the central region overlying an intercell region of the surface semiconductor layer, set between the body regions.

Abstract: A process for manufacturing a MOS device includes forming a semiconductor layer having a first type of conductivity; forming an insulated gate structure having an electrode region, above the semiconductor layer; forming body regions having a second type of conductivity, within the semiconductor layer, laterally and partially underneath the insulated gate structure; forming source regions having the first type of conductivity, within the body regions; and forming a first enrichment region, in a surface portion of the semiconductor layer underneath the insulated gate structure. The first enrichment region has the first type of conductivity and is set at a distance from the body regions. In order to form the first enrichment region, a first enrichment window is defined within the insulated gate structure, and first dopant species of the first type of conductivity are introduced through the first enrichment window and in a way self-aligned thereto.

Abstract: A process for manufacturing a MOS device includes forming a semiconductor layer having a first type of conductivity; forming an insulated gate structure having an electrode region, above the semiconductor layer; forming body regions having a second type of conductivity, within the semiconductor layer, laterally and partially underneath the insulated gate structure; forming source regions having the first type of conductivity, within the body regions; and forming a first enrichment region, in a surface portion of the semiconductor layer underneath the insulated gate structure. The first enrichment region has the first type of conductivity and is set at a distance from the body regions. In order to form the first enrichment region, a first enrichment window is defined within the insulated gate structure, and first dopant species of the first type of conductivity are introduced through the first enrichment window and in a way self-aligned thereto.

Abstract: An embodiment of a MOS device resistant to ionizing-radiation, has: a surface semiconductor layer with a first type of conductivity; a gate structure formed above the surface semiconductor layer, and constituted by a dielectric gate region and a gate-electrode region overlying the dielectric gate region; and body regions having a second type of conductivity, formed within the surface semiconductor layer, laterally and partially underneath the gate structure. In particular, the dielectric gate region is formed by a central region having a first thickness, and by side regions having a second thickness, smaller than the first thickness; the central region overlying an intercell region of the surface semiconductor layer, set between the body regions.

Abstract: A process for manufacturing a MOS device includes forming a semiconductor layer having a first type of conductivity; forming an insulated gate structure having an electrode region (25), above the semiconductor layer (23); forming body regions having a second type of conductivity, within the semiconductor layer, laterally and partially underneath the insulated gate structure; forming source regions having the first type of conductivity, within the body regions; and forming a first enrichment region, in a surface portion of the semiconductor layer underneath the insulated gate structure. The first enrichment region has the first type of conductivity and is set at a distance from the body regions. In order to form the first enrichment region, a first enrichment window is defined within the insulated gate structure, and first dopant species of the first type of conductivity are introduced through the first enrichment window and in a way self-aligned thereto.

Abstract: An embodiment of a MOS device resistant to ionizing-radiation, has: a surface semiconductor layer with a first type of conductivity; a gate structure formed above the surface semiconductor layer, and constituted by a dielectric gate region and a gate-electrode region overlying the dielectric gate region; and body regions having a second type of conductivity, formed within the surface semiconductor layer, laterally and partially underneath the gate structure. In particular, the dielectric gate region is formed by a central region having a first thickness, and by side regions having a second thickness, smaller than the first thickness; the central region overlying an intercell region of the surface semiconductor layer, set between the body regions.

Abstract: An embodiment of a MOS device resistant to ionizing-radiation, has: a surface semiconductor layer with a first type of conductivity; a gate structure formed above the surface semiconductor layer, and constituted by a dielectric gate region and a gate-electrode region overlying the dielectric gate region; and body regions having a second type of conductivity, formed within the surface semiconductor layer, laterally and partially underneath the gate structure. In particular, the dielectric gate region is formed by a central region having a first thickness, and by side regions having a second thickness, smaller than the first thickness; the central region overlying an intercell region of the surface semiconductor layer, set between the body regions.

Abstract: An embodiment of a MOS device resistant to ionizing-radiation, has: a surface semiconductor layer with a first type of conductivity; a gate structure formed above the surface semiconductor layer, and constituted by a dielectric gate region and a gate-electrode region overlying the dielectric gate region; and body regions having a second type of conductivity, formed within the surface semiconductor layer, laterally and partially underneath the gate structure. In particular, the dielectric gate region is formed by a central region having a first thickness, and by side regions having a second thickness, smaller than the first thickness; the central region overlying an intercell region of the surface semiconductor layer, set between the body regions.

Abstract: A process for manufacturing a MOS device includes forming a semiconductor layer having a first type of conductivity; forming an insulated gate structure having an electrode region (25), above the semiconductor layer (23); forming body regions having a second type of conductivity, within the semiconductor layer, laterally and partially underneath the insulated gate structure; forming source regions having the first type of conductivity, within the body regions; and forming a first enrichment region, in a surface portion of the semiconductor layer underneath the insulated gate structure. The first enrichment region has the first type of conductivity and is set at a distance from the body regions. In order to form the first enrichment region, a first enrichment window is defined within the insulated gate structure, and first dopant species of the first type of conductivity are introduced through the first enrichment window and in a way self-aligned thereto.

Abstract: An embodiment of a MOS device resistant to ionizing-radiation, has: a surface semiconductor layer with a first type of conductivity; a gate structure formed above the surface semiconductor layer, and constituted by a dielectric gate region and a gate-electrode region overlying the dielectric gate region; and body regions having a second type of conductivity, formed within the surface semiconductor layer, laterally and partially underneath the gate structure. In particular, the dielectric gate region is formed by a central region having a first thickness, and by side regions having a second thickness, smaller than the first thickness; the central region overlying an intercell region of the surface semiconductor layer, set between the body regions.

Abstract: A manufacturing method for a power device integrated on a semiconductor substrate with double thickness of a gate dielectric layer is described, which comprises the following steps: forming first dielectric portions having a first thickness; forming on the whole semiconductor substrate a first dielectric layer thinner than the first dielectric portions; forming a conductive layer on the first dielectric layer; forming a second dielectric layer on the conductive layer; performing an etching step of the second dielectric layer and of the conductive layer to form first spacers and a gate electrode, to define, between the gate electrode and the substrate, second dielectric portions in the first dielectric layer, the second dielectric portions being auto-aligned with the first portions.

Abstract: A process for forming a trench gate power MOS transistor includes forming an epitaxial layer having a first type of conductivity on a semiconductor substrate, and forming a body region having a second type of conductivity on the epitaxial layer. A gate trench is formed in the body region and in the epitaxial layer. The process further includes countersinking upper portions of the gate trench, and forming a gate dielectric layer on surfaces of the gate trench including the upper portions thereof. A gate conducting layer is formed on surfaces of the gate dielectric layer for defining a gate electrode. The gate conducting layer has a thickness that is insufficient for completely filling the gate trench so that a residual cavity remains therein. The residual cavity is filled with a filler layer. The gate conducting layer is removed from an upper surface of the body region while using the filler layer as a self-aligned mask. The edge surfaces of the gate conducting layer are oxidized.

Abstract: A manufacturing method for a power device integrated on a semiconductor substrate with double thickness of a gate dielectric layer is described, which comprises the following steps: forming first dielectric portions having a first thickness; forming on the whole semiconductor substrate a first dielectric layer thinner than the first dielectric portions; forming a conductive layer on the first dielectric layer; forming a second dielectric layer on the conductive layer; performing an etching step of the second dielectric layer and of the conductive layer to form first spacers and a gate electrode, to define, between the gate electrode and the substrate, second dielectric portions in the first dielectric layer, the second dielectric portions being auto-aligned with the first portions.

Abstract: A method of producing a protective inhibitor layer of moisture-generated corrosion for aluminum (Al) alloy metallization layers, particularly in semiconductor electronic devices, includes chemically treating the metallization layer in at least two steps using a mixture of concentrated nitric acid and trace phosphoric acid to produce a thin protective phosphate layer. Alternatively, the method may include dipping the electronic device at least once in a mixture of a polar organic solvent and phosphoric acid (H3PO4) or phosphate derivatives thereof in a low percentage amount (e.g., with a phosphate reactant such as orthophosphoric acid or even R—HxPOy, where R is an alkaline type of ion group or an alkyl radical). The thin film may be formed on top of a thin layer of native aluminum oxide hydrate Al2O3.xH2O.

Abstract: A process for fabricating a VDMOS power transistor includes forming a gate overlying at least one channel region in a semiconductor substrate, and forming spacers on a first portion of the semiconductor substrate self-aligned with the gate. A first dopant is implanted into the exposed portion of the semiconductor substrate for defining a body region of the transistor. The first dopant is implanted through a first implant window defined by the spacers. The spacers are removed, and a second dopant is implanted into the first portion of the semiconductor substrate for defining a source region of the transistor. The second dopant is implanted through a second implant window defined by an edge of the gate.

Abstract: A process for forming a trench gate power MOS transistor includes forming an epitaxial layer having a first type of conductivity on a semiconductor substrate, and forming a body region having a second type of conductivity on the epitaxial layer. A gate trench is formed in the body region and in the epitaxial layer. The process further includes countersinking upper portions of the gate trench, and forming a gate dielectric layer on surfaces of the gate trench including the upper portions thereof. A gate conducting layer is formed on surfaces of the gate dielectric layer for defining a gate electrode. The gate conducting layer has a thickness that is insufficient for completely filling the gate trench so that a residual cavity remains therein. The residual cavity is filled with a filler layer. The gate conducting layer is removed from an upper surface of the body region while using the filler layer as a self-aligned mask. The edge surfaces of the gate conducting layer are oxidized.

Abstract: A method of producing a protective inhibitor layer of moisture-generated corrosion for aluminum (Al) alloy metallization layers, particularly in semiconductor electronic devices, includes chemically treating the metallization layer in at least two steps using a mixture of concentrated nitric acid and trace phosphoric acid to produce a thin protective phosphate layer. Alternatively, the method may include dipping the electronic device at least once in a mixture of a polar organic solvent and phosphoric acid (H3PO4) or phosphate derivatives thereof in a low percentage amount (e.g., with a phosphate reactant such as orthophosphoric acid or even R—HxPOy, where R is an alkaline type of ion group or an alkyl radical). The thin film may be formed on top of a thin layer of native aluminum oxide hydrate Al2O3.xH2O.

Abstract: A method of producing a protective inhibitor layer of moisture-generated corrosion for aluminum (Al) alloy metallization layers, particularly in semiconductor electronic devices, includes chemically treating the metallization layer in at least two steps using a mixture of concentrated nitric acid and trace phosphoric acid to produce a thin protective phosphate layer. Alternatively, the method may include dipping the electronic device at least once in a mixture of a polar organic solvent and phosphoric acid (H3PO4) or phosphate derivatives thereof in a low percentage amount (e.g., with a phosphate reactant such as orthophosphoric acid or even R—HxPOy, where R is an alkaline type of ion group or an alkyl radical). The thin film may be formed on top of a thin layer of native aluminum oxide hydrate Al2O3.xH2O.