Patents by Inventor Giuseppe D'Arrigo
Giuseppe D'Arrigo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11837558Abstract: A process for manufacturing a strained semiconductor device envisages: providing a die of semiconductor material, in which elementary components of the semiconductor device have been integrated by means of initial front-end steps; and coupling, using the die-attach technique, the die to a support, at a coupling temperature. The aforesaid coupling step envisages selecting the value of the coupling temperature at a value higher than an operating temperature of use of the semiconductor device, and moreover selecting the material of the support so that it is different from the material of the die in order to determine, at the operating temperature, a coupling stress that is a function of the different values of the coefficients of thermal expansion of the materials of the die and of the support and of the temperature difference between the coupling temperature and the operating temperature.Type: GrantFiled: July 9, 2021Date of Patent: December 5, 2023Assignee: STMICROELECTRONICS S.r.l.Inventors: Santo Alessandro Smerzi, Michele Calabretta, Alessandro Sitta, Crocifisso Marco Antonio Renna, Giuseppe D'Arrigo
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Publication number: 20210335730Abstract: A process for manufacturing a strained semiconductor device envisages: providing a die of semiconductor material, in which elementary components of the semiconductor device have been integrated by means of initial front-end steps; and coupling, using the die-attach technique, the die to a support, at a coupling temperature. The aforesaid coupling step envisages selecting the value of the coupling temperature at a value higher than an operating temperature of use of the semiconductor device, and moreover selecting the material of the support so that it is different from the material of the die in order to determine, at the operating temperature, a coupling stress that is a function of the different values of the coefficients of thermal expansion of the materials of the die and of the support and of the temperature difference between the coupling temperature and the operating temperature.Type: ApplicationFiled: July 9, 2021Publication date: October 28, 2021Applicant: STMICROELECTRONICS S.r.l.Inventors: Santo Alessandro SMERZI, Michele CALABRETTA, Alessandro SITTA, Crocifisso Marco Antonio RENNA, Giuseppe D'ARRIGO
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Patent number: 11075172Abstract: A process for manufacturing a strained semiconductor device envisages: providing a die of semiconductor material, in which elementary components of the semiconductor device have been integrated by means of initial front-end steps; and coupling, using the die-attach technique, the die to a support, at a coupling temperature. The aforesaid coupling step envisages selecting the value of the coupling temperature at a value higher than an operating temperature of use of the semiconductor device, and moreover selecting the material of the support so that it is different from the material of the die in order to determine, at the operating temperature, a coupling stress that is a function of the different values of the coefficients of thermal expansion of the materials of the die and of the support and of the temperature difference between the coupling temperature and the operating temperature.Type: GrantFiled: April 19, 2019Date of Patent: July 27, 2021Assignee: STMICROELECTRONICS S.r.l.Inventors: Santo Alessandro Smerzi, Michele Calabretta, Alessandro Sitta, Crocifisso Marco Antonio Renna, Giuseppe D'Arrigo
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Patent number: 10475673Abstract: Various embodiments provide a reaction chamber including a support, a receptacle, and a sponge. The support includes a plurality of bars that are spaced from each other by a plurality of openings. Each of the bars has side surfaces that are slanted or tilted downward such that melted material may readily flow through the openings. The support is covered with a coating of silicon carbide to prevent materials from adhering to the support. The receptacle underlies the support and is configured to collect any melted material that is drained through the openings of the support. The sponge is positioned in the receptacle and under the support. The sponge is configured to absorb any melted material that is collected by the receptacle.Type: GrantFiled: September 26, 2017Date of Patent: November 12, 2019Assignee: STMICROELECTRONICS S.R.L.Inventors: Ruggero Anzalone, Nicolo Frazzetto, Aldo Raciti, Marco Antonio Salanitri, Giuseppe Abbondanza, Giuseppe D'Arrigo
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Publication number: 20190326231Abstract: A process for manufacturing a strained semiconductor device envisages: providing a die of semiconductor material, in which elementary components of the semiconductor device have been integrated by means of initial front-end steps; and coupling, using the die-attach technique, the die to a support, at a coupling temperature. The aforesaid coupling step envisages selecting the value of the coupling temperature at a value higher than an operating temperature of use of the semiconductor device, and moreover selecting the material of the support so that it is different from the material of the die in order to determine, at the operating temperature, a coupling stress that is a function of the different values of the coefficients of thermal expansion of the materials of the die and of the support and of the temperature difference between the coupling temperature and the operating temperature.Type: ApplicationFiled: April 19, 2019Publication date: October 24, 2019Inventors: Santo Alessandro SMERZI, Michele CALABRETTA, Alessandro SITTA, Crocifisso Marco Antonio RENNA, Giuseppe D'ARRIGO
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Publication number: 20180090350Abstract: Various embodiments provide a reaction chamber including a support, a receptacle, and a sponge. The support includes a plurality of bars that are spaced from each other by a plurality of openings. Each of the bars has side surfaces that are slanted or tilted downward such that melted material may readily flow through the openings. The support is covered with a coating of silicon carbide to prevent materials from adhering to the support. The receptacle underlies the support and is configured to collect any melted material that is drained through the openings of the support. The sponge is positioned in the receptacle and under the support. The sponge is configured to absorb any melted material that is collected by the receptacle.Type: ApplicationFiled: September 26, 2017Publication date: March 29, 2018Inventors: Ruggero ANZALONE, Nicolo FRAZZETTO, Aldo RACITI, Marco Antonio SALANITRI, Giuseppe ABBONDANZA, Giuseppe D'ARRIGO
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Patent number: 8304144Abstract: Fuel cells are formed in a single layer of conductive monocrystalline silicon including a succession of electrically isolated conductive silicon bodies separated by narrow parallel trenches etched through the whole thickness of the silicon layer. Semicells in a back-to-back configuration are formed over etch surfaces of the separation trenches. Each semicell formed on the etch surface of one of the silicon bodies forming an elementary cell in cooperation with an opposite semicell formed on the etch surface of the next silicon body of the succession, is separated by an ion exchange membrane resin filling the separation trench between the opposite semicells forming a solid electrolyte of the elementary cell. Each semicell includes a porous conductive silicon region permeable to fluids, extending for a certain depth from the etch surface of the silicon body, at least partially coated by a non passivable metallic material.Type: GrantFiled: May 4, 2010Date of Patent: November 6, 2012Assignee: STMicroelectronics S.R.L.Inventors: Giuseppe D'Arrigo, Salvatore Coffa
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Publication number: 20120122015Abstract: A micro fuel cell system comprises at least an anode region and a cathode region being realized in a substrate as well as at least an active area for chemical reactions and an ionic exchange membrane for separating the active area. The anode and cathode regions, the active area and the ionic exchange membrane are realized on a same planar surface being made by the substrate in order to form a single multifunctional bipolar plate.Type: ApplicationFiled: July 15, 2010Publication date: May 17, 2012Applicant: CONSIGLIO NAZIONALE DELLE RICERCHEInventors: Giuseppe D'Arrigo, Stefania Specchia, Ugo Icardi, Corrado Rosario Spinella, Emanuele Rimini, Guido Saracco
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Publication number: 20100216046Abstract: Fuel cells are formed in a single layer of conductive monocrystalline silicon including a succession of electrically isolated conductive silicon bodies separated by narrow parallel trenches etched through the whole thickness of the silicon layer. Semicells in a back-to-back configuration are formed over etch surfaces of the separation trenches. Each semicell formed on the etch surface of one of the silicon bodies forming an elementary cell in cooperation with an opposite semicell formed on the etch surface of the next silicon body of the succession, is separated by an ion exchange membrane resin filling the separation trench between the opposite semicells forming a solid electrolyte of the elementary cell. Each semicell includes a porous conductive silicon region permeable to fluids, extending for a certain depth from the etch surface of the silicon body, at least partially coated by a non passivable metallic material.Type: ApplicationFiled: May 4, 2010Publication date: August 26, 2010Applicant: STMicroelectronics S.r.l.Inventors: Giuseppe D'Arrigo, Salvatore Coffa
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Patent number: 7777285Abstract: A method is provided for fabricating a semiconductor device that includes a suspended micro-system. According to the method, a silicon porous layer is formed above a silicon substrate, and the silicon porous layer is oxidized. An oxide layer is deposited, and a first polysilicon layer is deposited above the oxide layer. The first polysilicon layer, the oxide layer, and the silicon porous layer are selectively removed. A nitride layer is deposited, and a second polysilicon layer is deposited. The second polysilicon layer, the nitride layer, the first polysilicon layer, and the oxide layer are selectively removed. The silicon porous layer is removed in areas made accessible by the previous step. Also provided is a semiconductor device that includes a suspended structure fixed to at least two walls through a plurality of hinges, with the suspended structure including an oxide layer, a first polysilicon layer, a nitride layer, and a second polysilicon layer.Type: GrantFiled: March 8, 2007Date of Patent: August 17, 2010Assignee: STMicroelectronics S.r.l.Inventors: Giuseppe D'Arrigo, Rosario Corrado Spinella
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Patent number: 7763372Abstract: Fuel cells are formed in a single layer of conductive monocrystalline silicon including a succession of electrically isolated conductive silicon bodies separated by narrow parallel trenches etched through the whole thickness of the silicon layer. Semicells in a back-to-back configuration are formed over etch surfaces of the separation trenches. Each semicell formed on the etch surface of one of the silicon bodies forming an elementary cell in cooperation with an opposite semicell formed on the etch surface of the next silicon body of the succession, is separated by an ion exchange membrane resin filling the separation trench between the opposite semicells forming a solid electrolyte of the elementary cell. Each semicell includes a porous conductive silicon region permeable to fluids, extending for a certain depth from the etch surface of the silicon body, at least partially coated by a non passivable metallic material.Type: GrantFiled: May 12, 2006Date of Patent: July 27, 2010Assignee: STMicroelectronics S.R.L.Inventors: Giuseppe D'Arrigo, Salvatore Coffa
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Publication number: 20070145501Abstract: A method is provided for fabricating a semiconductor device that includes a suspended micro-system. According to the method, a silicon porous layer is formed above a silicon substrate, and the silicon porous layer is oxidized. An oxide layer is deposited, and a first polysilicon layer is deposited above the oxide layer. The first polysilicon layer, the oxide layer, and the silicon porous layer are selectively removed. A nitride layer is deposited, and a second polysilicon layer is deposited. The second polysilicon layer, the nitride layer, the first polysilicon layer, and the oxide layer are selectively removed. The silicon porous layer is removed in areas made accessible by the previous step. Also provided is a semiconductor device that includes a suspended structure fixed to at least two walls through a plurality of hinges, with the suspended structure including an oxide layer, a first polysilicon layer, a nitride layer, and a second polysilicon layer.Type: ApplicationFiled: March 8, 2007Publication date: June 28, 2007Applicant: STMicroelectronics S.r.l.Inventors: Giuseppe D'Arrigo, Rosario Spinella
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Patent number: 7195946Abstract: A method is provided for fabricating a semiconductor device that includes a suspended micro-system. According to the method, a silicon porous layer is formed above a silicon substrate, and the silicon porous layer is oxidized. An oxide layer is deposited, and a first polysilicon layer is deposited above the oxide layer. The first polysilicon layer, the oxide layer, and the silicon porous layer are selectively removed. A nitride layer is deposited, and a second polysilicon layer is deposited. The second polysilicon layer, the nitride layer, the first polysilicon layer, and the oxide layer are selectively removed. The silicon porous layer is removed in areas made accessible by the previous step. Also provided is a semiconductor device that includes a suspended structure fixed to at least two walls through a plurality of hinges, with the suspended structure including an oxide layer, a first polysilicon layer, a nitride layer, and a second polysilicon layer.Type: GrantFiled: July 2, 2004Date of Patent: March 27, 2007Assignee: STMicroelectronics, S.r.L.Inventors: Giuseppe D'Arrigo, Rosario Corrado Spinella
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Publication number: 20060255464Abstract: Fuel cells are formed in a single layer of conductive monocrystalline silicon including a succession of electrically isolated conductive silicon bodies separated by narrow parallel trenches etched through the whole thickness of the silicon layer. Semicells in a back-to-back configuration are formed over etch surfaces of the separation trenches. Each semicell formed on the etch surface of one of the silicon bodies forming an elementary cell in cooperation with an opposite semicell formed on the etch surface of the next silicon body of the succession, is separated by an ion exchange membrane resin filling the separation trench between the opposite semicells forming a solid electrolyte of the elementary cell. Each semicell includes a porous conductive silicon region permeable to fluids, extending for a certain depth from the etch surface of the silicon body, at least partially coated by a non passivable metallic material.Type: ApplicationFiled: May 12, 2006Publication date: November 16, 2006Applicant: STMicroelectronics S.r.l.Inventors: Giuseppe D'Arrigo, Salvatore Coffa
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Patent number: 6969664Abstract: A fuel cell for an electrical load circuit includes a first monocrystalline silicon substrate and a positive half-cell formed therein, and a second monocrystalline silicon substrate and a positive half-cell formed therein. Each half-cell includes a microporous catalytic electrode permeable to a gas and connectable to the electrical load circuit. A cell area is defined on a surface of each respective monocrystalline silicon substrate, and includes a plurality of parallel trenches formed therein for receiving the gas to be fed to the respective microporous catalytic electrode. A cation exchange membrane separates the two microporous catalytic electrodes. Each half-cell includes a passageway for feeding the respective gas to the corresponding microporous catalytic electrode.Type: GrantFiled: May 16, 2002Date of Patent: November 29, 2005Assignee: STMicroelectronics S.r.l.Inventors: Giuseppe D'Arrigo, Salvatore Coffa, Rosario Corrado Spinella
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Publication number: 20050026321Abstract: A method is provided for fabricating a semiconductor device that includes a suspended micro-system. According to the method, a silicon porous layer is formed above a silicon substrate, and the silicon porous layer is oxidized. An oxide layer is deposited, and a first polysilicon layer is deposited above the oxide layer. The first polysilicon layer, the oxide layer, and the silicon porous layer are selectively removed. A nitride layer is deposited, and a second polysilicon layer is deposited. The second polysilicon layer, the nitride layer, the first polysilicon layer, and the oxide layer are selectively removed. The silicon porous layer is removed in areas made accessible by the previous step. Also provided is a semiconductor device that includes a suspended structure fixed to at least two walls through a plurality of hinges, with the suspended structure including an oxide layer, a first polysilicon layer, a nitride layer, and a second polysilicon layer.Type: ApplicationFiled: July 2, 2004Publication date: February 3, 2005Applicant: STMICROELECTRONICS S.r.l.Inventors: Giuseppe D'Arrigo, Rosario Spinella
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Patent number: 6506658Abstract: A method for fabricating a silicon-on-insulator (SOI) wafer that includes a monocrystalline silicon substrate with a doped region buried therein is provided. The method includes forming a plurality of trench-like openings extending from a surface of the substrate to the doped buried region, and selectively etching through the plurality of trench-like openings to change the doped buried region into a porous silicon region. The porous silicon region is oxidized to obtain an insulating region for the SOI wafer.Type: GrantFiled: December 29, 2000Date of Patent: January 14, 2003Assignee: STMicroelectronics S.r.l.Inventors: Giuseppe D'Arrigo, Corrado Spinella, Salvatore Coffa, Giuseppe Arena, Marco Camalleri
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Publication number: 20030003347Abstract: A fuel cell for an electrical load circuit includes a first monocrystalline silicon substrate and a positive half-cell formed therein, and a second monocrystalline silicon substrate and a positive half-cell formed therein. Each half-cell includes a microporous catalytic electrode permeable to a gas and connectable to the electrical load circuit. A cell area is defined on a surface of each respective monocrystalline silicon substrate, and includes a plurality of parallel trenches formed therein for receiving the gas to be fed to the respective microporous catalytic electrode. A cation exchange membrane separates the two microporous catalytic electrodes. Each half-cell includes a passageway for feeding the respective gas to the corresponding microporous catalytic electrode.Type: ApplicationFiled: May 16, 2002Publication date: January 2, 2003Applicant: STMicroelectronics S.r.l.Inventors: Giuseppe D'Arrigo, Salvatore Coffa, Rosario Corrado Spinella
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Publication number: 20010023094Abstract: A method for fabricating a silicon-on-insulator (SOI) wafer that includes a monocrystalline silicon substrate with a doped region buried therein is provided. The method includes forming a plurality of trench-like openings extending from a surface of the substrate to the doped buried region, and selectively etching through the plurality of trench-like openings to change the doped buried region into a porous silicon region. The porous silicon region is oxidized to obtain an insulating region for the SOI wafer.Type: ApplicationFiled: December 29, 2000Publication date: September 20, 2001Applicant: STMicroelectronics S.r.l.Inventors: Giuseppe D'Arrigo, Corrado Spinella, Salvatore Coffa, Giuseppe Arena, Marco Camalleri