Abstract: A monitoring circuit performing logical and temporal task monitoring of a plurality of tasks comprises a task recording circuit and a task management circuit receiving as input a plurality of task signals, each task signal being indicative of an execution state of a respective task. The task management circuit comprises a managing circuit configured to operate in at least three modes depending on a respective event corresponding to either detection of a rising edge of a given task signal, occurrence of a trigger signal, or detection of a falling edge of a given task signal being monitored. In each mode the managing circuit is configured to check whether a variable representing the operation state of the task contains an expected value corresponding to the occurrence of the event enabling the respective mode, and output a result of the check operation in an error signal for the given task being monitored.

Abstract: Methods, systems, and devices for adaptive block mapping are described. In some examples, a first superblock and a second superblock may be established across one or more dice of a memory device. The superblocks may each include one or more blocks from a plurality of planes of a memory die. In some examples, the second superblock may include at least one bad block (e.g., defective block) in addition to one or more good blocks (e.g., non-defective blocks). The memory device may receive a command for writing data in a first mode and may write a first subset of the data to the first superblock in the first mode, a second subset of the data to the second superblock in the first mode, and one or more blocks associated with the second superblock in a second mode. Additionally or alternatively, the memory device may receive a second command for writing data in the second mode and may write the data to the first superblock in the first mode.

Abstract: A multi-composite electrochemical cell substantially consists of a thin polymer membrane including three different adjacent sectors, which are made of the same appropriately seamlessly modified polymer, incorporating in the polymer one or more conductive phases, or conductive fillers, such as graphene, metal, or a combination thereof. In the first sector the polymer material incorporates graphene nanoplatelets and acts as a cathode; in the second sector, interposed between the other two, the polymer material acts as an insulating spacer; in the third sector the polymer material incorporates graphene nanoplatelets and a metal filler or immersed metal contact rheophore, with negative standard reduction potential, and acts as an anode; wherein the metal filler is in the form of dispersed powder or dispersed flakes, or of a thin sheet incorporated in the polymer.

Abstract: Methods, systems, and devices for setting switching for single-level cells (SLCs) are described. A memory system may receive an access command from a host. The access command may correspond to an SLC block or to a multiple-level cell block. If the access command corresponds to an SLC block, the memory system may modify the access command to include one or more bits indicating a setting to use for performing the access operation corresponding to the access command. The setting may define one or more operating parameters for performing the access operation. The memory system may use bits to indicate the setting that are used to indicate a page address for multiple-level cell blocks. The memory system may issue the access command to a memory device, which may perform the access operation using the setting indicated in the one or more bits included by the memory system.

Abstract: Methods, systems, and devices for integrating a pivot table in a logical-to-physical mapping of a memory system are described. The memory system may receive a read command and read a first entry of a first subset of mapping and a second entry of a second subset of mapping. The second entry may include at least a portion of a pivot table associated with physical addresses of a non-volatile memory device. The memory system may retrieve data from a physical address identified in the pivot table, rather than access a different portion of the logical-to-physical mapping. The memory system may transmit, to a host system, the data retrieved from the physical address identified in the pivot table.

Abstract: A method for controlling a BLDC motor includes controlling the rotational speed or position of the BLDC motor based on a position of the rotor of the motor. The BLDC motor is driven by a three-phase inverter. A PWM signal is generated for three PWM phases, each including a pair of complementary signals with dead-time and having a duty cycle based on the current position of the rotor. The complementary signals are supplied to a respective high side and low side switch of each of three arms of the three-phase inverter, and a zero-crossing time measurement is performed on each of the back electromotive forces. Corresponding signals are obtained indicating the zero-crossing times. Trigger signals are generated, and the occurrence of a time interval corresponding to the dead time in the respective PWM phase is identified. The zero-crossing time measurement is performed during the occurrence of the dead-time.

Abstract: Methods, systems, and devices for data relocation operation techniques are described. A memory system may include blocks of memory cells, for example, within a non-volatile memory device of the memory system. The memory system may identify a command to perform a data relocation operation associated with a block of memory cells and may select between a first procedure and a second procedure for performing the data relocation operation. The memory system may select between the first procedure and the second procedure based on whether one or more parameters associated with the data relocation operation satisfy a threshold. For example, the memory system may select the first procedure if the one or more parameters satisfy the threshold and may select the second procedure if the one or more parameters do not satisfy the threshold. The memory system may perform the data relocation operation using the selected procedure.

Abstract: Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.

Abstract: A gas turbine engine includes a fan located at a forward portion of the gas turbine engine, and a compressor section and a turbine section arranged in serial flow order. The compressor section and the turbine section together define a core airflow path. A rotary member is rotatable with the fan and with a low pressure turbine of the turbine section. The low pressure turbine includes a rotating drum to which a first airfoil structure is connected and extends radially inward toward the rotary member. A torque frame connects the rotating drum to the rotary member and transfers torque from the first airfoil structure mounted to the rotating drum to the rotary member. The torque frame includes an inner disk mounted to the rotary member, an outer ring and a second airfoil structure formed separately from the outer ring and connected thereto by a releasable connecting structure. The second airfoil structure extends radially inward from the outer ring toward the inner disk.

Abstract: Methods, systems, and devices for integrating a pivot table in a logical-to-physical mapping of a memory system are described. The memory system may receive a read command and read a first entry of a first subset of mapping and a second entry of a second subset of mapping. The second entry may include at least a portion of a pivot table associated with physical addresses of a non-volatile memory device. The memory system may retrieve data from a physical address identified in the pivot table, rather than access a different portion of the logical-to-physical mapping. The memory system may transmit, to a host system, the data retrieved from the physical address identified in the pivot table.

Abstract: Methods, systems, and devices for memory operations are described. A memory system may write data to sequential physical addresses of the memory system based on receiving multiple write commands, where the sequential physical addresses may be associated with sequential logical addresses. Based on writing the data, the memory system may receive a read command for data stored in the memory system, where the read command may include a logical address. The memory system may determine a physical address of the memory system where the data is stored based on the received logical address, a last logical address written at the memory system, and a sequence number group associated with the last logical address. Based on determining the physical address, the memory system may read the data stored at the physical address.

Abstract: A method for forming a graphene layer on a semiconductor substrate, a semiconductor diode utilizing the method for graphene layer formation, and an optoelectronic semiconductor device also utilizing the method for graphene layer formation are provided. An example method for disposing a graphene layer on a semiconductor substrate may include depositing a metal catalyst layer on a top surface of the semiconductor substrate and patterning the metal catalyst layer, such that one or more portions of the top surface of the semiconductor substrate are covered by one or more metal catalyst layer structures. The method may further include facilitating a graphene growth process on an exposed surface of the one or more metal catalyst layer structures, wherein the graphene growth process forms the graphene layer on the exposed surfaces of the one or more metal catalyst layer structures.

Abstract: Methods, systems, and devices for setting switching for single-level cells (SLCs) are described. A memory system may receive an access command from a host. The access command may correspond to an SLC block or to a multiple-level cell block. If the access command corresponds to an SLC block, the memory system may modify the access command to include one or more bits indicating a setting to use for performing the access operation corresponding to the access command. The setting may define one or more operating parameters for performing the access operation. The memory system may use bits to indicate the setting that are used to indicate a page address for multiple-level cell blocks. The memory system may issue the access command to a memory device, which may perform the access operation using the setting indicated in the one or more bits included by the memory system.

Abstract: Devices and techniques for corrupted storage portion recovery in a memory device are described herein. A failure event can be detected during a garbage collection operation on a collection of storage portions (e.g., pages) in a memory array. Here, members of the collection of storage portions are being moved from a former physical location to a new physical location by the garbage collection operation. A reference to a former physical location of a possibly corrupt storage portion in the collection of storage portions can be retrieved in response to the failure event. Here, the possibly corrupt storage portion has already been written to a new physical location as part of the garbage collection operation. The possibly corrupt storage portion can then be rewritten at the new physical location using data from the former physical location.

Abstract: A multi-composite electrochemical cell substantially consists of a thin polymer membrane including three different adjacent sectors, which are made of the same appropriately seamlessly modified polymer, incorporating in the polymer one or more conductive phases, or conductive fillers, such as graphene, metal, or a combination thereof. In the first sector the polymer material incorporates graphene nanoplatelets and acts as a cathode; in the second sector, interposed between the other two, the polymer material acts as an insulating spacer; in the third sector the polymer material incorporates graphene nanoplatelets and a metal filler or immersed metal contact rheophore, with negative standard reduction potential, and acts as an anode; wherein the metal filler is in the form of dispersed powder or dispersed flakes, or of a thin sheet incorporated in the polymer.

Abstract: Methods, systems, and devices for memory operations are described. A memory system may write data to sequential physical addresses of the memory system based on receiving multiple write commands, where the sequential physical addresses may be associated with sequential logical addresses. Based on writing the data, the memory system may receive a read command for data stored in the memory system, where the read command may include a logical address. The memory system may determine a physical address of the memory system where the data is stored based on the received logical address, a last logical address written at the memory system, and a sequence number group associated with the last logical address. Based on determining the physical address, the memory system may read the data stored at the physical address.

Abstract: Methods, systems, and devices for adaptive block mapping are described. In some examples, a first superblock and a second superblock may be established across one or more dice of a memory device. The superblocks may each include one or more blocks from a plurality of planes of a memory die. In some examples, the second superblock may include at least one bad block (e.g., defective block) in addition to one or more good blocks (e.g., non-defective blocks). The memory device may receive a command for writing data in a first mode and may write a first subset of the data to the first superblock in the first mode, a second subset of the data to the second superblock in the first mode, and one or more blocks associated with the second superblock in a second mode. Additionally or alternatively, the memory device may receive a second command for writing data in the second mode and may write the data to the first superblock in the first mode.

Abstract: Methods, systems, and devices for data relocation operation techniques are described. A memory system may include blocks of memory cells, for example, within a non-volatile memory device of the memory system. The memory system may identify a command to perform a data relocation operation associated with a block of memory cells and may select between a first procedure and a second procedure for performing the data relocation operation. The memory system may select between the first procedure and the second procedure based on whether one or more parameters associated with the data relocation operation satisfy a threshold. For example, the memory system may select the first procedure if the one or more parameters satisfy the threshold and may select the second procedure if the one or more parameters do not satisfy the threshold. The memory system may perform the data relocation operation using the selected procedure.

Abstract: Devices and techniques for corrupted storage portion recovery in a memory device are described herein. A failure event can be detected during a garbage collection operation on a collection of storage portions (e.g., pages) in a memory array. Here, members of the collection of storage portions are being moved from a former physical location to a new physical location by the garbage collection operation. A reference to a former physical location of a possibly corrupt storage portion in the collection of storage portions can be retrieved in response to the failure event. Here, the possibly corrupt storage portion has already been written to a new physical location as part of the garbage collection operation. The possibly corrupt storage portion can then be rewritten at the new physical location using data from the former physical location.

Abstract: Devices and techniques for NAND logical-to-physical table region tracking are described herein. A write request, including a logical page and data to be written at the logical page, is received at a controller of a NAND device. The NAND controller may then establish an entry in a logical-to-physical (L2P) mapping table between the logical page and a physical page of a physical block of the NAND device to which the data is written. Here, the entry may be in a region of the L2P mapping table that is one of multiple regions. An indication of the region may be written in a data structure corresponding to the physical block.