Patents by Inventor Giuseppe D'Arrigo

Giuseppe D'Arrigo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11837558
    Abstract: A process for manufacturing a strained semiconductor device envisages: providing a die of semiconductor material, in which elementary components of the semiconductor device have been integrated by means of initial front-end steps; and coupling, using the die-attach technique, the die to a support, at a coupling temperature. The aforesaid coupling step envisages selecting the value of the coupling temperature at a value higher than an operating temperature of use of the semiconductor device, and moreover selecting the material of the support so that it is different from the material of the die in order to determine, at the operating temperature, a coupling stress that is a function of the different values of the coefficients of thermal expansion of the materials of the die and of the support and of the temperature difference between the coupling temperature and the operating temperature.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: December 5, 2023
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Santo Alessandro Smerzi, Michele Calabretta, Alessandro Sitta, Crocifisso Marco Antonio Renna, Giuseppe D'Arrigo
  • Publication number: 20210335730
    Abstract: A process for manufacturing a strained semiconductor device envisages: providing a die of semiconductor material, in which elementary components of the semiconductor device have been integrated by means of initial front-end steps; and coupling, using the die-attach technique, the die to a support, at a coupling temperature. The aforesaid coupling step envisages selecting the value of the coupling temperature at a value higher than an operating temperature of use of the semiconductor device, and moreover selecting the material of the support so that it is different from the material of the die in order to determine, at the operating temperature, a coupling stress that is a function of the different values of the coefficients of thermal expansion of the materials of the die and of the support and of the temperature difference between the coupling temperature and the operating temperature.
    Type: Application
    Filed: July 9, 2021
    Publication date: October 28, 2021
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Santo Alessandro SMERZI, Michele CALABRETTA, Alessandro SITTA, Crocifisso Marco Antonio RENNA, Giuseppe D'ARRIGO
  • Patent number: 11075172
    Abstract: A process for manufacturing a strained semiconductor device envisages: providing a die of semiconductor material, in which elementary components of the semiconductor device have been integrated by means of initial front-end steps; and coupling, using the die-attach technique, the die to a support, at a coupling temperature. The aforesaid coupling step envisages selecting the value of the coupling temperature at a value higher than an operating temperature of use of the semiconductor device, and moreover selecting the material of the support so that it is different from the material of the die in order to determine, at the operating temperature, a coupling stress that is a function of the different values of the coefficients of thermal expansion of the materials of the die and of the support and of the temperature difference between the coupling temperature and the operating temperature.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: July 27, 2021
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Santo Alessandro Smerzi, Michele Calabretta, Alessandro Sitta, Crocifisso Marco Antonio Renna, Giuseppe D'Arrigo
  • Patent number: 10475673
    Abstract: Various embodiments provide a reaction chamber including a support, a receptacle, and a sponge. The support includes a plurality of bars that are spaced from each other by a plurality of openings. Each of the bars has side surfaces that are slanted or tilted downward such that melted material may readily flow through the openings. The support is covered with a coating of silicon carbide to prevent materials from adhering to the support. The receptacle underlies the support and is configured to collect any melted material that is drained through the openings of the support. The sponge is positioned in the receptacle and under the support. The sponge is configured to absorb any melted material that is collected by the receptacle.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: November 12, 2019
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Ruggero Anzalone, Nicolo Frazzetto, Aldo Raciti, Marco Antonio Salanitri, Giuseppe Abbondanza, Giuseppe D'Arrigo
  • Publication number: 20190326231
    Abstract: A process for manufacturing a strained semiconductor device envisages: providing a die of semiconductor material, in which elementary components of the semiconductor device have been integrated by means of initial front-end steps; and coupling, using the die-attach technique, the die to a support, at a coupling temperature. The aforesaid coupling step envisages selecting the value of the coupling temperature at a value higher than an operating temperature of use of the semiconductor device, and moreover selecting the material of the support so that it is different from the material of the die in order to determine, at the operating temperature, a coupling stress that is a function of the different values of the coefficients of thermal expansion of the materials of the die and of the support and of the temperature difference between the coupling temperature and the operating temperature.
    Type: Application
    Filed: April 19, 2019
    Publication date: October 24, 2019
    Inventors: Santo Alessandro SMERZI, Michele CALABRETTA, Alessandro SITTA, Crocifisso Marco Antonio RENNA, Giuseppe D'ARRIGO
  • Publication number: 20180090350
    Abstract: Various embodiments provide a reaction chamber including a support, a receptacle, and a sponge. The support includes a plurality of bars that are spaced from each other by a plurality of openings. Each of the bars has side surfaces that are slanted or tilted downward such that melted material may readily flow through the openings. The support is covered with a coating of silicon carbide to prevent materials from adhering to the support. The receptacle underlies the support and is configured to collect any melted material that is drained through the openings of the support. The sponge is positioned in the receptacle and under the support. The sponge is configured to absorb any melted material that is collected by the receptacle.
    Type: Application
    Filed: September 26, 2017
    Publication date: March 29, 2018
    Inventors: Ruggero ANZALONE, Nicolo FRAZZETTO, Aldo RACITI, Marco Antonio SALANITRI, Giuseppe ABBONDANZA, Giuseppe D'ARRIGO
  • Patent number: 8304144
    Abstract: Fuel cells are formed in a single layer of conductive monocrystalline silicon including a succession of electrically isolated conductive silicon bodies separated by narrow parallel trenches etched through the whole thickness of the silicon layer. Semicells in a back-to-back configuration are formed over etch surfaces of the separation trenches. Each semicell formed on the etch surface of one of the silicon bodies forming an elementary cell in cooperation with an opposite semicell formed on the etch surface of the next silicon body of the succession, is separated by an ion exchange membrane resin filling the separation trench between the opposite semicells forming a solid electrolyte of the elementary cell. Each semicell includes a porous conductive silicon region permeable to fluids, extending for a certain depth from the etch surface of the silicon body, at least partially coated by a non passivable metallic material.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: November 6, 2012
    Assignee: STMicroelectronics S.R.L.
    Inventors: Giuseppe D'Arrigo, Salvatore Coffa
  • Publication number: 20120122015
    Abstract: A micro fuel cell system comprises at least an anode region and a cathode region being realized in a substrate as well as at least an active area for chemical reactions and an ionic exchange membrane for separating the active area. The anode and cathode regions, the active area and the ionic exchange membrane are realized on a same planar surface being made by the substrate in order to form a single multifunctional bipolar plate.
    Type: Application
    Filed: July 15, 2010
    Publication date: May 17, 2012
    Applicant: CONSIGLIO NAZIONALE DELLE RICERCHE
    Inventors: Giuseppe D'Arrigo, Stefania Specchia, Ugo Icardi, Corrado Rosario Spinella, Emanuele Rimini, Guido Saracco
  • Publication number: 20100216046
    Abstract: Fuel cells are formed in a single layer of conductive monocrystalline silicon including a succession of electrically isolated conductive silicon bodies separated by narrow parallel trenches etched through the whole thickness of the silicon layer. Semicells in a back-to-back configuration are formed over etch surfaces of the separation trenches. Each semicell formed on the etch surface of one of the silicon bodies forming an elementary cell in cooperation with an opposite semicell formed on the etch surface of the next silicon body of the succession, is separated by an ion exchange membrane resin filling the separation trench between the opposite semicells forming a solid electrolyte of the elementary cell. Each semicell includes a porous conductive silicon region permeable to fluids, extending for a certain depth from the etch surface of the silicon body, at least partially coated by a non passivable metallic material.
    Type: Application
    Filed: May 4, 2010
    Publication date: August 26, 2010
    Applicant: STMicroelectronics S.r.l.
    Inventors: Giuseppe D'Arrigo, Salvatore Coffa
  • Patent number: 7777285
    Abstract: A method is provided for fabricating a semiconductor device that includes a suspended micro-system. According to the method, a silicon porous layer is formed above a silicon substrate, and the silicon porous layer is oxidized. An oxide layer is deposited, and a first polysilicon layer is deposited above the oxide layer. The first polysilicon layer, the oxide layer, and the silicon porous layer are selectively removed. A nitride layer is deposited, and a second polysilicon layer is deposited. The second polysilicon layer, the nitride layer, the first polysilicon layer, and the oxide layer are selectively removed. The silicon porous layer is removed in areas made accessible by the previous step. Also provided is a semiconductor device that includes a suspended structure fixed to at least two walls through a plurality of hinges, with the suspended structure including an oxide layer, a first polysilicon layer, a nitride layer, and a second polysilicon layer.
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: August 17, 2010
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giuseppe D'Arrigo, Rosario Corrado Spinella
  • Patent number: 7763372
    Abstract: Fuel cells are formed in a single layer of conductive monocrystalline silicon including a succession of electrically isolated conductive silicon bodies separated by narrow parallel trenches etched through the whole thickness of the silicon layer. Semicells in a back-to-back configuration are formed over etch surfaces of the separation trenches. Each semicell formed on the etch surface of one of the silicon bodies forming an elementary cell in cooperation with an opposite semicell formed on the etch surface of the next silicon body of the succession, is separated by an ion exchange membrane resin filling the separation trench between the opposite semicells forming a solid electrolyte of the elementary cell. Each semicell includes a porous conductive silicon region permeable to fluids, extending for a certain depth from the etch surface of the silicon body, at least partially coated by a non passivable metallic material.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: July 27, 2010
    Assignee: STMicroelectronics S.R.L.
    Inventors: Giuseppe D'Arrigo, Salvatore Coffa
  • Publication number: 20070145501
    Abstract: A method is provided for fabricating a semiconductor device that includes a suspended micro-system. According to the method, a silicon porous layer is formed above a silicon substrate, and the silicon porous layer is oxidized. An oxide layer is deposited, and a first polysilicon layer is deposited above the oxide layer. The first polysilicon layer, the oxide layer, and the silicon porous layer are selectively removed. A nitride layer is deposited, and a second polysilicon layer is deposited. The second polysilicon layer, the nitride layer, the first polysilicon layer, and the oxide layer are selectively removed. The silicon porous layer is removed in areas made accessible by the previous step. Also provided is a semiconductor device that includes a suspended structure fixed to at least two walls through a plurality of hinges, with the suspended structure including an oxide layer, a first polysilicon layer, a nitride layer, and a second polysilicon layer.
    Type: Application
    Filed: March 8, 2007
    Publication date: June 28, 2007
    Applicant: STMicroelectronics S.r.l.
    Inventors: Giuseppe D'Arrigo, Rosario Spinella
  • Patent number: 7195946
    Abstract: A method is provided for fabricating a semiconductor device that includes a suspended micro-system. According to the method, a silicon porous layer is formed above a silicon substrate, and the silicon porous layer is oxidized. An oxide layer is deposited, and a first polysilicon layer is deposited above the oxide layer. The first polysilicon layer, the oxide layer, and the silicon porous layer are selectively removed. A nitride layer is deposited, and a second polysilicon layer is deposited. The second polysilicon layer, the nitride layer, the first polysilicon layer, and the oxide layer are selectively removed. The silicon porous layer is removed in areas made accessible by the previous step. Also provided is a semiconductor device that includes a suspended structure fixed to at least two walls through a plurality of hinges, with the suspended structure including an oxide layer, a first polysilicon layer, a nitride layer, and a second polysilicon layer.
    Type: Grant
    Filed: July 2, 2004
    Date of Patent: March 27, 2007
    Assignee: STMicroelectronics, S.r.L.
    Inventors: Giuseppe D'Arrigo, Rosario Corrado Spinella
  • Publication number: 20060255464
    Abstract: Fuel cells are formed in a single layer of conductive monocrystalline silicon including a succession of electrically isolated conductive silicon bodies separated by narrow parallel trenches etched through the whole thickness of the silicon layer. Semicells in a back-to-back configuration are formed over etch surfaces of the separation trenches. Each semicell formed on the etch surface of one of the silicon bodies forming an elementary cell in cooperation with an opposite semicell formed on the etch surface of the next silicon body of the succession, is separated by an ion exchange membrane resin filling the separation trench between the opposite semicells forming a solid electrolyte of the elementary cell. Each semicell includes a porous conductive silicon region permeable to fluids, extending for a certain depth from the etch surface of the silicon body, at least partially coated by a non passivable metallic material.
    Type: Application
    Filed: May 12, 2006
    Publication date: November 16, 2006
    Applicant: STMicroelectronics S.r.l.
    Inventors: Giuseppe D'Arrigo, Salvatore Coffa
  • Patent number: 6969664
    Abstract: A fuel cell for an electrical load circuit includes a first monocrystalline silicon substrate and a positive half-cell formed therein, and a second monocrystalline silicon substrate and a positive half-cell formed therein. Each half-cell includes a microporous catalytic electrode permeable to a gas and connectable to the electrical load circuit. A cell area is defined on a surface of each respective monocrystalline silicon substrate, and includes a plurality of parallel trenches formed therein for receiving the gas to be fed to the respective microporous catalytic electrode. A cation exchange membrane separates the two microporous catalytic electrodes. Each half-cell includes a passageway for feeding the respective gas to the corresponding microporous catalytic electrode.
    Type: Grant
    Filed: May 16, 2002
    Date of Patent: November 29, 2005
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giuseppe D'Arrigo, Salvatore Coffa, Rosario Corrado Spinella
  • Publication number: 20050026321
    Abstract: A method is provided for fabricating a semiconductor device that includes a suspended micro-system. According to the method, a silicon porous layer is formed above a silicon substrate, and the silicon porous layer is oxidized. An oxide layer is deposited, and a first polysilicon layer is deposited above the oxide layer. The first polysilicon layer, the oxide layer, and the silicon porous layer are selectively removed. A nitride layer is deposited, and a second polysilicon layer is deposited. The second polysilicon layer, the nitride layer, the first polysilicon layer, and the oxide layer are selectively removed. The silicon porous layer is removed in areas made accessible by the previous step. Also provided is a semiconductor device that includes a suspended structure fixed to at least two walls through a plurality of hinges, with the suspended structure including an oxide layer, a first polysilicon layer, a nitride layer, and a second polysilicon layer.
    Type: Application
    Filed: July 2, 2004
    Publication date: February 3, 2005
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Giuseppe D'Arrigo, Rosario Spinella
  • Patent number: 6506658
    Abstract: A method for fabricating a silicon-on-insulator (SOI) wafer that includes a monocrystalline silicon substrate with a doped region buried therein is provided. The method includes forming a plurality of trench-like openings extending from a surface of the substrate to the doped buried region, and selectively etching through the plurality of trench-like openings to change the doped buried region into a porous silicon region. The porous silicon region is oxidized to obtain an insulating region for the SOI wafer.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: January 14, 2003
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giuseppe D'Arrigo, Corrado Spinella, Salvatore Coffa, Giuseppe Arena, Marco Camalleri
  • Publication number: 20030003347
    Abstract: A fuel cell for an electrical load circuit includes a first monocrystalline silicon substrate and a positive half-cell formed therein, and a second monocrystalline silicon substrate and a positive half-cell formed therein. Each half-cell includes a microporous catalytic electrode permeable to a gas and connectable to the electrical load circuit. A cell area is defined on a surface of each respective monocrystalline silicon substrate, and includes a plurality of parallel trenches formed therein for receiving the gas to be fed to the respective microporous catalytic electrode. A cation exchange membrane separates the two microporous catalytic electrodes. Each half-cell includes a passageway for feeding the respective gas to the corresponding microporous catalytic electrode.
    Type: Application
    Filed: May 16, 2002
    Publication date: January 2, 2003
    Applicant: STMicroelectronics S.r.l.
    Inventors: Giuseppe D'Arrigo, Salvatore Coffa, Rosario Corrado Spinella
  • Publication number: 20010023094
    Abstract: A method for fabricating a silicon-on-insulator (SOI) wafer that includes a monocrystalline silicon substrate with a doped region buried therein is provided. The method includes forming a plurality of trench-like openings extending from a surface of the substrate to the doped buried region, and selectively etching through the plurality of trench-like openings to change the doped buried region into a porous silicon region. The porous silicon region is oxidized to obtain an insulating region for the SOI wafer.
    Type: Application
    Filed: December 29, 2000
    Publication date: September 20, 2001
    Applicant: STMicroelectronics S.r.l.
    Inventors: Giuseppe D'Arrigo, Corrado Spinella, Salvatore Coffa, Giuseppe Arena, Marco Camalleri