Patents by Inventor Giuseppe Di Gregorio

Giuseppe Di Gregorio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6815964
    Abstract: The present invention relates to method to improve RF measurements accuracy on an automatic testing equipment (ATE) for IC wafers by implementing a test board de-embedding phase, wherein each wafer includes a device under test located on a wafer die plane and being contacted by probecard needles of a probecard that is coupled to a configuration board through a probe interface board (PIB), the method including the following phases: performing an automatic calibration phase of the testing equipment up to an internal plane located inside the automatic testing equipment; performing a calibration plane transfer up to a plane of the configuration board using a predetermined number of calibration standard loads realized on the wafer; performing a test boards de-embedding phase up to the wafer die plane.
    Type: Grant
    Filed: December 26, 2001
    Date of Patent: November 9, 2004
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giuseppe Di Gregorio, Maria Luisa Gambina, Biagio Russo
  • Patent number: 6757632
    Abstract: A method is provided for testing an integrated circuit in an automatic test environment. According to the method, the automatic test environment is set up, and there is performed a repetitive measurement of at least one electrical quantity representative of an integrated circuit response to a set of prescribed integrated circuit test conditions. The automatic test environment is reset, and the integrated circuit test conditions are changed in synchrony with a synchronization signal having a prescribed periodicity, so that all of the measurements are allotted a time slot of the same length. Also provided is an automatic test equipment apparatus that includes a synchronization generator for supplying a synchronization signal having a prescribed periodicity to means for putting the integrated circuit in a set test condition. The means changes the set test condition in synchrony with the synchronization signal, so that all of the measurements are allotted a time slot of the same length.
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: June 29, 2004
    Assignee: STMicroelectronics S.r.L.
    Inventors: Giuseppe Tuttobene, Giuseppe Di Gregorio, Biagio Russo
  • Publication number: 20020198674
    Abstract: A method is provided for testing an integrated circuit in an automatic test environment. According to the method, the automatic test environment is set up, and there is performed a repetitive measurement of at least one electrical quantity representative of an integrated circuit response to a set of prescribed integrated circuit test conditions. The automatic test environment is reset, and the integrated circuit test conditions are changed in synchrony with a synchronization signal having a prescribed periodicity, so that all of the measurements are allotted a time slot of the same length. Also provided is an automatic test equipment apparatus for testing an integrated circuit. The apparatus includes a synchronization generator for supplying a synchronization signal having a prescribed periodicity to means for putting the integrated circuit in a set test condition. The means changes the set test condition in synchrony with the synchronization signal.
    Type: Application
    Filed: June 20, 2002
    Publication date: December 26, 2002
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Giuseppe Tuttobene, Giuseppe Di Gregorio, Biagio Russo
  • Publication number: 20020167304
    Abstract: The present invention relates to method to improve RF measurements accuracy on an automatic testing equipment (ATE) for IC wafers by implementing a test board de-embedding phase, wherein each wafer includes a device under test located on a wafer die plane and being contacted by probecard needles of a probecard that is coupled to a configuration board through a probe interface board (PIB), the method including the following phases: performing an automatic calibration phase of the testing equipment up to an internal plane located inside the automatic testing equipment; performing a calibration plane transfer up to a plane of the configuration board using a predetermined number of calibration standard loads realized on the wafer; performing a test boards de-embedding phase up to the wafer die plane.
    Type: Application
    Filed: December 26, 2001
    Publication date: November 14, 2002
    Applicant: STMicroelectronics S.r.l.
    Inventors: Giuseppe Di Gregorio, Maria Luisa Gambina, Biagio Russo