Abstract: Devices and techniques for NAND logical-to-physical table region tracking are described herein. A write request, including a logical page and data to be written at the logical page, is received at a controller of a NAND device. The NAND controller may then establish an entry in a logical-to-physical (L2P) mapping table between the logical page and a physical page of a physical block of the NAND device to which the data is written. Here, the entry may be in a region of the L2P mapping table that is one of multiple regions. An indication of the region may be written in a data structure corresponding to the physical block.

Abstract: Devices and techniques for synchronizing NAND logical-to-physical table region tracking are described herein. Table region data structures for physical blocks are maintained. These structures include logical-to-physical (L2P) mapping table portions that point to the respective physical blocks. When garbage collection is performed on a block, table region structures for that block, and another (e.g., the next block to be garbage collected) are read to avoid loading L2P table regions that do not point to the block. If any of the read portions of the L2P table region fail to point to either the block or the other block, these L2P table portions are removed from the loaded table region data structures.

Abstract: Devices and techniques for synchronizing NAND logical-to-physical table region tracking are described herein. Table region data structures for physical blocks are maintained. These structures include logical-to-physical (L2P) mapping table portions that point to the respective physical blocks. When garbage collection is performed on a block, table region structures for that block, and another (e.g., the next block to be garbage collected) are read to avoid loading L2P table regions that do not point to the block. If any of the read portions of the L2P table region fail to point to either the block or the other block, these L2P table portions are removed from the loaded table region data structures.

Abstract: Devices and techniques for synchronizing NAND logical-to-physical table region tracking are described herein. Table region data structures for physical blocks are maintained. These structures include logical-to-physical (L2P) mapping table portions that point to the respective physical blocks. When garbage collection is performed on a block, table region structures for that block, and another (e.g., the next block to be garbage collected) are read to avoid loading L2P table regions that do not point to the block. If any of the read portions of the L2P table region fail to point to either the block or the other block, these L2P table portions are removed from the loaded table region data structures.

Abstract: A method includes responding to a wear-level operation request by copying data from a first portion of a first memory array to a second portion of the first memory array, and copying metadata associated with the data from a third portion of a second memory array to a fourth portion of the second memory array. The first memory array includes a NAND or NAND-based memory array, and the second memory array includes non-volatile memory including at least one of the group consisting of: phase-change memory, EEPROM, and NOR flash memory.

Abstract: A method includes responding to a wear-level operation request by copying data from a first portion of a first memory array to a second portion of the first memory array, and copying metadata associated with the data from a third portion of a second memory array to a fourth portion of the second memory array. The first memory array includes a NAND or NAND-based memory array, and the second memory array includes non-volatile memory including at least one of the group consisting of: phase-change memory, EEPROM, and NOR flash memory.

Abstract: A method includes responding to a wear-level operation request by copying data from a first portion of a first memory array to a second portion of the first memory array, and copying metadata associated with the data from a third portion of a second memory array to a fourth portion of the second memory array. The first memory array includes a NAND or NAND-based memory array, and the second memory array includes non-volatile memory including at least one of the group consisting of: phase-change memory, EEPROM, and NOR flash memory.

Abstract: A network model for the planning and/or the provisioning of traffic flows in a communication network includes nodes interconnected with each other by links according to a given network topology. The network model uses a graph defined by arc objects storing information related to both the links and adjacent nodes thereof.

Abstract: Subject matter disclosed herein relates to sub-block accessible cache memory.

Abstract: Subject matter disclosed herein relates to sub-block accessible cache memory.

Abstract: Apparatus and methods for caching data are disclosed. Data is stored in a non-sub-block accessible nonvolatile memory, such as a NAND flash. A portion of the stored data is cached in a cache implemented using phase change memory using a sub-block accessible address.

Abstract: Subject matter disclosed herein relates to sub-block accessible cache memory.

Abstract: Subject matter disclosed herein relates to storing information via a NAND flash translation layer.

Abstract: A network model for the planning and/or the provisioning of traffic flows in a communication network includes nodes interconnected with each other by links according to a given network topology. The network model uses a graph defined by arc objects storing information related to both the links and adjacent nodes thereof.

Abstract: A procedure for sorting a plurality of circuit data flows (7, 8, . . . ) located, according to an initial configuration, in a plurality of sets of slots (space, time, frequency or wavelength) in a transport sub-network, comprising the following steps:—calculating a theoretical configuration in which flows are optimised in terms of occupied band by applying a theoretical flow routing algorithm; on the basis of the theoretical configuration defined above, exchanging the position of the flows in the sub-network slots to obtain an optimal arrangement which minimises the occupied slots; flows whose position corresponds to the position assumed by the flows in the initial position are identified to reduce the number of exchanges; defining and implementing a minimum shift sequence of single flows needed to shift each single flow from an initial position occupied in the initial flow configuration to a final position corresponding to the position assumed by the flow in the optimal slot set arrangement.

Abstract: A procedure for sorting a plurality of circuit data flows (7, 8, . . . ) located, according to an initial configuration, in a plurality of sets of slots (space, time, frequency or wavelength) in a transport sub-network, comprising the following steps:—calculating a theoretical configuration in which flows are optimised in terms of occupied band by applying a theoretical flow routing algorithm; on the basis of the theoretical configuration defined above, exchanging the position of the flows in the sub-network slots to obtain an optimal arrangement which minimises the occupied slots; flows whose position corresponds to the position assumed by the flows in the initial position are identified to reduce the number of exchanges; defining and implementing a minimum shift sequence of single flows needed to shift each single flow from an initial position occupied in the initial flow configuration to a final position corresponding to the position assumed by the flow in the optimal slot set arrangement.

Abstract: In a ring network communication structure for communication on an optical carrier (3A, 3B), a plurality of nodes (2A, . . . , 2E) are interconnected by means of connections comprising at least a first (3A) and a second (3B) optical carrier, such as an optical fiber. Transmission occurs on the ring according to a WDM scheme, by utilizing a first wavelength (.lambda..sub.1) for communication in one direction on the first carrier (3A) of said pair, while communication in the opposite direction occurs by employing a second wavelength (.lambda..sub.2) on the other optical carrier (3B). In the presence of a failure on one of the connections, the nodes adjacent (2B, 2C) to the failed connection reconfigure themselves to ensure the continuation of communication on the alternative path provided by the ring, by utilizing the first wavelength (.lambda..sub.1) on the second carrier (3B) and the second wavelength (.lambda..sub.2)on the first carrier (3A). Preferential application to SDH optical fiber ring networks.

Abstract: A process for preparing hydrocarbonaceous resins from C.sub.5 fractions is disclosed in which the starting hydrocarbonaceous fraction is enriched with cis-piperylene. A catalyst system is also disclosed for the formation of the resins by polymerization and the simplest catalyst is an aluminum halide. In other embodiments, the aluminum halide is used together with a second component such as a hydrocarbyl halide and/or a halide of a metal selected from Sn, Si, B, Ti, Pb, Sb, As and others. Resins having improved physico-chemical properties are obtained.

Abstract: Oligomers are obtained from straight-chain alpha olefins by contacting these with a catalytic system of the binary type, which is composed of an organic metallic compound of aluminum and a haloid acid. Subsequent hydrogenation of the oligomers is carried out in order to remove possible residual unsaturations.

Abstract: This invention relates to the preparation of linear alpha-olefin oligomers and more particularly to the catalyst system which consists of a two component mixture comprising an aluminium halide and a compound capable of reacting with said aluminium halide and selected among(a) halogens or interhalogenic compounds,(b) halogenated compounds having the formula ##STR1## in which R', R", R'", represent H or alkyl or aryl (C) METAL HALIDESBy the above catalyst system oligomers can be prepared with high yields and with an easier control and performance of the reaction, starting from linear alpha-olefins having 3 to 12 carbon atoms.