Abstract: A method for determining prospective peering partners for an internet service provider, includes gathering internet service provider's routing and traffic information; gathering additional routing information from sources other than the internet service provider; identifying uncovered target autonomous systems based on the internet service provider's routing and traffic information, the uncovered target autonomous systems being autonomous systems with non-null traffic and that are reachable by the internet service provider via a transit relationship; identifying paths from the internet service provider to the uncovered target autonomous systems based on the additional routing information; identifying intermediate autonomous systems along the identified paths; and determining at least a prospective peering partner for the internet service provider based on the identified intermediate autonomous systems.

Abstract: A method for determining prospective peering partners for an internet service provider, includes gathering internet service provider's routing and traffic information; gathering additional routing information from sources other than the internet service provider; identifying uncovered target autonomous systems based on the internet service provider's routing and traffic information, the uncovered target autonomous systems being autonomous systems with non-null traffic and that are reachable by the internet service provider via a transit relationship; identifying paths from the internet service provider to the uncovered target autonomous systems based on the additional routing information; identifying intermediate autonomous systems along the identified paths; and determining at least a prospective peering partner for the internet service provider based on the identified intermediate autonomous systems.

Abstract: For the benefit of a reference ISP having a number of users, connectivity evaluations on a data communication network are performed relative to one or more ISPs of interest. Upon selecting a plurality of autonomous systems capable of forming a traffic source and/or destination for the users of the reference provider, tables of the BGP type are provided containing information on the paths available on the network for routing the traffic with regard to the above-mentioned autonomous systems. From these tables the paths of BGP type are extracted for the respective provider or providers of interest, searching for the paths that contain the respective AS number for the provider and/or providers of interest. For each autonomous system the oriented subpaths are extracted between each said autonomous system and the provider or providers of interest, identifying for each subpath the respective number of hops.

Abstract: or the benefit of a reference ISP (10) having a number of users (C), connectivity evaluations on a data communication network are performed in relation to one or more ISPs of interest (12, 14). Upon selecting a plurality (T) of autonomous systems (AS) capable of forming a traffic source and/or destination for the users (C) of the reference provider (10), tables of the BGP type (BGP1, . . . , BGPm) are provided containing information on the paths available on the network for routing the traffic with regard to the above-mentioned autonomous systems (AS). From said tables the paths of BGP type are extracted relating to the provider or providers of interest (12, 14), searching for the paths that contain the respective AS number for the provider and/or providers of interest (12, 14). For each autonomous system (AS) the oriented sub-paths are extracted between each said autonomous system (AS) and the provider or providers of interest (12, 14), identifying for each sub-path the relating number of hops.

Abstract: A semiconductor device includes a transistor junction formed in a substrate adjacent to an isolation region. A region between the transistor junction and the isolation region includes an area susceptible to hot carrier effects. The transistor junction extends from a surface of the substrate to a first depth. A buried conductive channel layer is formed within the transistor junction between the surface of the substrate and the first depth. The buried conductive channel layer has a peak conduction depth, which is different from a depth of the area susceptible to hot carrier effects.

Abstract: A semiconductor device includes a transistor junction formed in a substrate adjacent to an isolation region. A region between the transistor junction and the isolation region includes an area susceptible to hot carrier effects. The transistor junction extends from a surface of the substrate to a first depth. A buried conductive channel layer is formed within the transistor junction between the surface of the substrate and the first depth. The buried conductive channel layer has a peak conduction depth, which is different from a depth of the area susceptible to hot carrier effects.

Abstract: An on-chip circuit and testing method to quantify a transistor charge transfer performance and charge retention capability of a DRAM cell in a realistic operational environment is described. The method and circuit can be extended to evaluate aging of the cell transfer device due to MOSFET wearout mechanisms that become activate during the charge transfer as well as during storage under operating or burn-in conditions. The on-chip circuit forces and senses a voltage to an individual DRAM storage capacitor allowing the pulse test methodology characterize the individual storage capacitor charge leakage rate and quantify the rate of charge transfer between the bitline and the storage capacitor in the DRAM cell.

Abstract: A dynamic random access memory (DRAM) formed in a semiconductor body has individual pairs of memory cells that are isolated from one another by a vertical electrical isolation trench and are isolated from support circuitry. The isolation trench has sidewalls and upper and lower portions, and encircles an area of the semiconductor body which contains the memory cells. This electrically isolates pairs of memory cells from each other and from the support circuitry contained within the semiconductor body but not located within the encircled area. The lower portion of the isolation trench is filled with an electrically conductive material that has sidewall portions thereof which are at least partly separated from the sidewalls of the lower portion of the trench by a first electrical insulator, and that has a lower portion that is in electrical contact with the semiconductor body. The upper portion of the isolation trench is filled with a second electrical insulator.

Abstract: An on-chip circuit and testing method to quantify a transistor charge transfer performance and charge retention capability of a DRAM cell in a realistic operational environment is described. The method and circuit can be extended to evaluate aging of the cell transfer device due to MOSFET wearout mechanisms that become activate during the charge transfer as well as during storage under operating or burn-in conditions. The on-chip circuit forces and senses a voltage to an individual DRAM storage capacitor, allowing the pulse test methodology characterize the individual storage capacitor charge leakage rate and quantify the rate of charge transfer between the bitline and the storage capacitor in the DRAM cell.

Abstract: A semiconductor device and method of manufacturing the same are provided. A trench is formed in a semiconductor substrate. A thin oxide liner is preferably formed on surfaces of the trench. After formation of the oxide liner, first regions of the semiconductor substrate are masked, leaving second regions thereof exposed. N-type devices are to be formed in the first regions and p-type devices are to be formed in the second regions. N-type ions may then be implanted into sidewalls of the trenches in the second regions. The mask is stripped and formation of the semiconductor device may be carried out in a conventional manner. The n-type ions are preferably only implanted into sidewalls where PMOSFETs are formed.