Patents by Inventor Giuseppe Maruccia

Giuseppe Maruccia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10540277
    Abstract: A method comprising: receiving a transaction associated with an address and having a transaction destination, said address being in an interleaved region of a memory; determining one of a plurality of destinations for said transaction, different parts of said interleaved memory region being respectively accessible by said plurality of destinations; and associating routing information to said transaction, said routing information associated with the determined destination.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: January 21, 2020
    Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS S.R.L.
    Inventors: Michael Soulie, Riccardo Locatelli, Valerio Catalano, Giuseppe Maruccia, Giuseppe Guarnaccia, Raffaele Guarrasi
  • Patent number: 10419432
    Abstract: An apparatus has a data store configured to store access activity information. The access activity information indicates which one or more of a plurality of different access parameter sets is active. The data store is also configured to store access defining information, which defines, at least for each active access parameter set, a number of channels, location information of said channels, and interleaving information associated with said channels.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: September 17, 2019
    Assignees: STMicroelectronics SA, STMicroelectronics (Grenoble2) SAS, STMicroelectronics S.R.L.
    Inventors: Michael Soulie, Riccardo Locatelli, Valerio Catalano, Hajer Ferjani, Giuseppe Maruccia, Raffaele Guarrasi, Giuseppe Guarnaccia
  • Publication number: 20160246714
    Abstract: A method comprising: receiving a transaction associated with an address and having a transaction destination, said address being in an interleaved region of a memory; determining one of a plurality of destinations for said transaction, different parts of said interleaved memory region being respectively accessible by said plurality of destinations; and associating routing information to said transaction, said routing information associated with the determined destination.
    Type: Application
    Filed: October 15, 2014
    Publication date: August 25, 2016
    Inventors: Michael Soulie, Riccardo Locatelli, Valerio Catalano, Giuseppe Maruccia, Giuseppe Guarnaccia, Raffaele Guarrasi
  • Publication number: 20160226878
    Abstract: An apparatus has a data store configured to store access activity information. The access activity information indicates which one or more of a plurality of different access parameter sets is active. The data store is also configured to store access defining information, which defines, at least for each active access parameter set, a number of channels, location information of said channels, and interleaving information associated with said channels.
    Type: Application
    Filed: October 17, 2014
    Publication date: August 4, 2016
    Inventors: Michael Soulie, Riccardo Locatelli, Valerio Catalano, Hajer Ferjani, Giuseppe Maruccia, Raffaele Guarrasi, Giuseppe Guarnaccia
  • Patent number: 8352628
    Abstract: A method is for transferring data from a source target to a destination target in a network. The method includes sending at least one request packet for the destination target, with the request packet containing information relating to a first address where data are located and a second address where data are to be stored. Moreover, at least one transaction request is sent to the source target, with the read request being elaborated from information contained in the request packet. The source target transfers the data located at the first address to the second address.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: January 8, 2013
    Assignee: STMicroelectronics SA
    Inventors: Giuseppe Maruccia, Riccardo Locatelli, Lorenzo Pieralisi, Marcello Coppola
  • Patent number: 8165120
    Abstract: This method for transferring data through a network on chip (NoC) between a first electronic device and a second electronic device, comprising: retrieving from the first device request packets comprising request control data for controlling data transfer and actual request data to be transferred; storing said request control and data to be transferred in memory means provided in an network interface (NI); and elaborating data packets to be transferred to the second device through said network, said data packets comprising a header and a payload elaborated from said control data and said actual data, respectively; The control data and the actual data to be transferred are stored in separate first and second memory means.
    Type: Grant
    Filed: November 10, 2008
    Date of Patent: April 24, 2012
    Assignee: STMicroelectronics (Grenoble) SAS
    Inventors: Giuseppe Maruccia, Riccardo Locatelli, Lorenzo Pieralisi, Marcello Coppola
  • Patent number: 7861018
    Abstract: A system for transmitting data includes a transmitter module, a receiver module and a channel provided with a flow control link between the transmitter and receiver modules. The channel provides a first control signal from the transmitter module to the receiver module, and a second control signal from the receiver module to the transmitter module for initiating data transmission. The transmitter or receiver module includes a synchronizer for synchronizing the first and second control signals.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: December 28, 2010
    Assignee: STMicroelectronics SA
    Inventors: Philippe Teninge, Riccardo Locatelli, Marcello Coppola, Lorenzo Pieralisi, Giuseppe Maruccia
  • Patent number: 7724735
    Abstract: A bandwidth allocator to allocate in real time shared resources of a network on-chip is disclosed. The bandwidth allocator routes data packets between elements of the network in response to requests to access the shared resources. The bandwidth allocator could include a plurality of network interfaces to process the data packets to be routed within the network and a plurality of routers for routing the data packets through the network. A processor, distributed within the routers, controls the routers and the transmission of each data of the data packets through the routers to provide a bandwidth for each data flow. The network interfaces is adapted to fill a header field of each data packet with header field information depending on a requested bandwidth. The processor controls the transmission of the data packets through the routers as a function of the value of the header field information of each data packet.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: May 25, 2010
    Assignee: STMicroelectronics SA
    Inventors: Riccardo Locatelli, Marcello Coppola, Giuseppe Maruccia, Lorenzo Pieralisi
  • Patent number: 7555001
    Abstract: A system for routing a data packet between N elements includes N network interfaces respectively connected to the N elements, with N being an even integer, and an on-chip packet-switched communication network arranged in a ring structure. The packet-switched communication network includes N routers respectively connected to the N interfaces, and N pairs of opposite uni-directional ring links. Each pair of ring links couples two adjacent routers in the ring structure, and each ring link provides two virtual channels. There are N/2 pairs of opposite uni-directional crossing links, with each pair of crossing links coupling two diametrically opposite routers in the ring structure.
    Type: Grant
    Filed: June 21, 2005
    Date of Patent: June 30, 2009
    Assignee: STMicroelectronics SA
    Inventors: Marcello Coppola, Riccardo Locatelli, Giuseppe Maruccia, Lorenzo Pieralisi
  • Publication number: 20090147783
    Abstract: This method for transferring data through a network on chip (NoC) between a first electronic device and a second electronic device, comprising: retrieving from the first device request packets comprising request control data for controlling data transfer and actual request data to be transferred; storing said request control and data to be transferred in memory means provided in an network interface (NI); and elaborating data packets to be transferred to the second device through said network, said data packets comprising a header and a payload elaborated from said control data and said actual data, respectively; The control data and the actual data to be transferred are stored in separate first and second memory means.
    Type: Application
    Filed: November 10, 2008
    Publication date: June 11, 2009
    Applicant: STMicroelectronics (Grenoble) SAS
    Inventors: Giuseppe Maruccia, Riccardo Locatelli, Lorenzo Pieralisi, Marcello Coppola
  • Publication number: 20090129390
    Abstract: Systems and methods for transferring a stream of at least one data packet between a first electronic device and second electronic device through a network-on-chip are disclosed. These systems and methods can comprise storing data packets in memory means provided in a network interface and transferring data packets from the memory means to the second electronic device. Packets can be transferred from the memory means after a quantity of packets is stored in the memory means, the quantity of packets being determined according to a value of a control parameter.
    Type: Application
    Filed: November 19, 2008
    Publication date: May 21, 2009
    Applicants: STMicroelectronics (Grenoble) SAS
    Inventors: Giuseppe Maruccia, Riccardo Locatelli, Lorenzo Pieralisi, Marcello Coppola, Michele Casula, Luca Fanucci, Sergio Saponara
  • Publication number: 20080320161
    Abstract: A method is for transferring data from a source target to a destination target in a network. The method includes sending at least one request packet for the destination target, with the request packet containing information relating to a first address where data are located and a second address where data are to be stored. Moreover, at least one transaction request is sent to the source target, with the read request being elaborated from information contained in the request packet. The source target transfers the data located at the first address to the second address.
    Type: Application
    Filed: June 20, 2008
    Publication date: December 25, 2008
    Applicant: STMicroelectronics SA
    Inventors: Giuseppe Maruccia, Riccardo Locatelli, Lorenzo Pieralisi, Marcello Coppola
  • Publication number: 20080155142
    Abstract: A system for transmitting data includes a transmitter module, a receiver module and a channel provided with a flow control link between the transmitter and receiver modules. The channel provides a first control signal from the transmitter module to the receiver module, and a second control signal from the receiver module to the transmitter module for initiating data transmission. The transmitter or receiver module includes a synchronizer for synchronizing the first and second control signals.
    Type: Application
    Filed: December 18, 2007
    Publication date: June 26, 2008
    Applicant: STMicroelectronics SA
    Inventors: Philippe Teninge, Riccardo Locatelli, Marcello Coppola, Lorenzo Pieralisi, Giuseppe Maruccia
  • Publication number: 20070274331
    Abstract: A bandwidth allocator to allocate in real time shared resources of a network on-chip is disclosed. The bandwidth allocator routes data packets between elements of the network in response to requests to access the shared resources. The bandwidth allocator could include a plurality of network interfaces to process the data packets to be routed within the network and a plurality of routers for routing the data packets through the network. A processor, distributed within the routers, controls the routers and the transmission of each data of the data packets through the routers to provide a bandwidth for each data flow. The network interfaces is adapted to fill a header field of each data packet with header field information depending on a requested bandwidth. The processor controls the transmission of the data packets through the routers as a function of the value of the header field information of each data packet.
    Type: Application
    Filed: May 24, 2007
    Publication date: November 29, 2007
    Applicant: STMicroelectronics SA
    Inventors: Riccardo Locatelli, Marcello Coppola, Giuseppe Maruccia, Lorenzo Pieralisi
  • Publication number: 20050286543
    Abstract: A system for routing a data packet between N elements includes N network interfaces respectively connected to the N elements, with N being an even integer, and an on-chip packet-switched communication network arranged in a ring structure. The packet-switched communication network includes N routers respectively connected to the N interfaces, and N pairs of opposite uni-directional ring links. Each pair of ring links couples two adjacent routers in the ring structure, and each ring link provides two virtual channels. There are N/2 pairs of opposite uni-directional crossing links, with each pair of crossing links coupling two diametrically opposite routers in the ring structure.
    Type: Application
    Filed: June 21, 2005
    Publication date: December 29, 2005
    Applicant: STMicroelectronics SA
    Inventors: Marcello Coppola, Riccardo Locatelli, Giuseppe Maruccia, Lorenzo Pieralisi