Abstract: Speech synthesis is selectable in two modes: "normal" mode in which the synthesis filter is responsive to prestored parameters, and "test" mode which executes a checking procedure based on test words from an outside source. Each mode has corresponding instructions prestored in a memory.

Abstract: A circuit arrangement for deciding concurrent requests for access to a common data bus emitted by a number n=2.sup.m of components of different ranks, specifically multiprocessor elements, comprises n mutually identical arbitration devices respectively associated with these components. The arbitration devices are interconnected in a chain by a priority bus of branched binary structure divided into m lines connected, within each device, to a logic network that is also connected to an internal m-conductor bus extending from a priority-code register. The priority bus, whose lines are normally at zero potential, is connected in any given device to the register thereof in the presence of an access request from the associated component whereupon its logic network determines whether the code on that bus equals the contents of the register; if so, the associated component is enabled by a control unit of the device to access the data bus.