Abstract: A system includes a processing circuit and a circuit configured to output a given number N of bits of configuration information to be used by the processing circuit. The circuit includes a non-volatile programmable memory configured to output a first group of N bits, N terminals for receiving a second group of N bits, and N logic gates. A first input terminal of each logic gate is connected to a respective bit of output from the non-volatile programmable memory and wherein a second input terminal of each logic gate is connected to a respective terminal of the N terminals.

Abstract: A system includes a processing circuit and a circuit configured to output a given number N of bits of configuration information to be used by the processing circuit. The circuit includes a non-volatile programmable memory configured to output a first group of N bits, N terminals for receiving a second group of N bits, and N logic gates. A first input terminal of each logic gate is connected to a respective bit of output from the non-volatile programmable memory and wherein a second input terminal of each logic gate is connected to a respective terminal of the N terminals.

Abstract: A receiver circuit extracts data from a serial data signal. The serial data signal contains a data packet having a first format with a first number of bits or a second format with a second number of bits based on a selection signal. The second format comprises the bits of the first format followed by one or more additional bits. The receiver circuit has at least one shift register having a total number of bits equal or greater than the number of bits of the second format and a switching circuit that selectively connects the serial data signal to one of the shift register serial inputs as a function of the selection signal. When the first format is selected and the respective bits received, the bits are stored in given positions of the one or more shift registers. The switching circuit also, when the second format is selected and the respective bits received, stores the bits of the first format included at the beginning of the second format in the same given positions of the one or more shift registers.

Abstract: A system includes a processing circuit and a circuit configured to output a given number N of bits of configuration information to be used by the processing circuit. The circuit includes a non-volatile programmable memory configured to output a first group of N bits, N terminals for receiving a second group of N bits, and N logic gates. A first input terminal of each logic gate is connected to a respective bit of output from the non-volatile programmable memory and wherein a second input terminal of each logic gate is connected to a respective terminal of the N terminals.

Abstract: A system includes a processing circuit and a circuit configured to output a given number N of bits of configuration information to be used by the processing circuit. The circuit includes a non-volatile programmable memory configured to output a first group of N bits, N terminals for receiving a second group of N bits, and N logic gates. A first input terminal of each logic gate is connected to a respective bit of output from the non-volatile programmable memory and wherein a second input terminal of each logic gate is connected to a respective terminal of the N terminals.

Abstract: A receiver circuit extracts data from a serial data signal. The serial data signal contains a data packet having a first format with a first number of bits or a second format with a second number of bits based on a selection signal. The second format comprises the bits of the first format followed by one or more additional bits. The receiver circuit has at least one shift register having a total number of bits equal or greater than the number of bits of the second format and a switching circuit that selectively connects the serial data signal to one of the shift register serial inputs as a function of the selection signal. When the first format is selected and the respective bits received, the bits are stored in given positions of the one or more shift registers. The switching circuit also, when the second format is selected and the respective bits received, stores the bits of the first format included at the beginning of the second format in the same given positions of the one or more shift registers.

Abstract: Errors induced by noise pulses in digital electronic circuits clocked with a clock signal are detected by providing at least one additional clock signal offset in time with respect to the clock signal by a given interval, and performing for at least one component of the circuit a comparison of correspondence between two versions of one and the same signal. The comparison is clocked by the additional clock signal and the absence of correspondence between the two versions of said signal identifies an error induced in the circuit by a noise pulse.

Abstract: A data cache memory coupled to a processor including processor clusters are adapted to operate simultaneously on scalar and vectorial data by providing data locations in the data cache memory for storing data for processing. The data locations are accessed either in a scalar mode or in a vectorial mode. This is done by explicitly mapping the data locations that are scalar and the data locations that are vectorial.

Abstract: A processor architecture for multimedia applications includes processor clusters providing vectorial data processing capability. Processing elements in the processor clusters process both data with a bit length N and data with bit lengths N/2, N/4, and so on according to a Single Instruction Multiple Data (SIMD) function. A load unit loads into the processor clusters data to be processed according to a same instruction. An intercluster data path exchanges data between the processor clusters. The intercluster data path is scalable to activate selected processor clusters. The processor operates simultaneously on SIMD, scalar and vectorial data.

Abstract: Digital signals are transmitted on a bus at given instants selectively in a non-encoded format and an encoded format. The decision whether to transmit the signals in non-encoded format or in encoded format is taken in part, based on a comparison of the signal to be transmitted on the bus for an instant of the aforesaid given instants with the signal transmitter on the bus for the preceding instant, so as to minimize switching activity on the bus.

Abstract: Errors induced by noise pulses in digital electronic circuits clocked with a clock signal are detected by providing at least one additional clock signal offset in time with respect to the clock signal by a given interval, and performing for at least one component of the circuit a comparison of correspondence between two versions of one and the same signal. The comparison is clocked by the additional clock signal and the absence of correspondence between the two versions of said signal identifies an error induced in the circuit by a noise pulse.

Abstract: A processor architecture includes a number of processing elements for treating input signals. The architecture is organized according to a matrix including rows and columns, the columns of which each include at least one microprocessor block having a computational part and a set of associated processing elements that are able to receive the same input signals. The number of associated processing elements is selectively variable in the direction of the column so as to exploit the parallelism of said signals. Additionally the processor architecture of the present invention enable dynamic switching between instruction parallelism and data parallel processing typical of vectorial functionality. The architecture can be scaled in various dimensions in an optimal configuration for the algorithm to be executed.

Abstract: A processor architecture includes a number of processing elements for treating input signals. The architecture is organized according to a matrix including rows and columns, the columns of which each include at least one microprocessor block having a computational part and a set of associated processing elements that are able to receive the same input signals. The number of associated processing elements is selectively variable in the direction of the column so as to exploit the parallelism of said signals. Additionally the processor architecture of the present invention enable dynamic switching between instruction parallelism and data parallel processing typical of vectorial functionality. The architecture can be scaled in various dimensions in an optimal configuration for the algorithm to be executed.

Abstract: Digital signals are transmitted on a bus at given instants selectively in a non-encoded format and an encoded format. The decision whether to transmit the signals in non-encoded format or in encoded format is taken in part, based on a comparison of the signal to be transmitted on the bus for an instant of the aforesaid given instants with the signal transmitter on the bus for the preceding instant, so as to minimize switching activity on the bus.

Abstract: Digital signals are transmitted on a bus at given instants selectively in a non-encoded format and an encoded format. The decision whether to transmit the signals in non-encoded format or in encoded format is taken in part, based on a comparison of the signal to be transmitted on the bus for an instant of the aforesaid given instants with the signal transmitter on the bus for the preceding instant, so as to minimize switching activity on the bus.

Abstract: A method for transmitting on an optical connection an input data sequence having first and second logic states, includes encoding the input data sequence prior to transmission on the optical connection, where the encoding minimizes the first logic states in the encoded data sequence. The encoding includes: arranging the input data sequence in parallel on a number of bus lines; counting the first logic states in the input data sequence; comparing the counting result with a value equal to half of the lines; and logically inverting the input data sequence on the lines if the counting result is greater than half of the lines of the input data sequence. The method further includes: ordering values of the input data sequence; identifying the first value having the first logic state; and applying the encoding operation just to the ordered values subsequent to the first value having the first logic state.

Abstract: A data cache memory coupled to a processor including processor clusters are adapted to operate simultaneously on scalar and vectorial data by providing data locations in the data cache memory for storing data for processing. The data locations are accessed either in a scalar mode or in a vectorial mode. This is done by explicitly mapping the data locations that are scalar and the data locations that are vectorial.

Abstract: A processor architecture for multimedia applications includes processor clusters providing vectorial data processing capability. Processing elements in the processor clusters process both data with a bit length N and data with bit lengths N/2, N/4, and so on according to a Single Instruction Multiple Data (SIMD) function. A load unit loads into the processor clusters data to be processed according to a same instruction. An intercluster data path exchanges data between the processor clusters. The intercluster data path is scalable to activate selected processor clusters. The processor operates simultaneously on SIMD, scalar and vectorial data.

Abstract: A processor architecture includes a number of processing elements for treating input signals. The architecture is organized according to a matrix including rows and columns, the columns of which each include at least one microprocessor block having a computational part and a set of associated processing elements that are able to receive the same input signals. The number of associated processing elements is selectively variable in the direction of the column so as to exploit the parallelism of said signals. The architecture can be scaled in various dimensions in an optimal configuration for the algorithm to be executed.

Abstract: A method for transmitting on an optical connection an input data sequence having first and second logic states, includes encoding the input data sequence prior to transmission on the optical connection, where the encoding minimizes the first logic states in the encoded data sequence. The encoding includes: arranging the input data sequence in parallel on a number of bus lines; counting the first logic states in the input data sequence; comparing the counting result with a value equal to half of the lines; and logically inverting the input data sequence on the lines if the counting result is greater than half of the lines of the input data sequence. The method further includes: ordering values of the input data sequence; identifying the first value having the first logic state; and applying the encoding operation just to the ordered values subsequent to the first value having the first logic state.