Abstract: A first signal path having an amplifier and a second signal path having an amplifier with adjustable gain factor are provided. A signal applied to the first and second signal paths is amplified and demodulated on the first signal path. Concurrently, the signal is amplified on the second signal path with a gain factor, and a power of the signal amplified by the second signal path is determined and used for determining the gain factor. A signal conditioning circuit has first and second signal paths and a first and a second operating state. In the first operating state, the first signal path is arranged for amplification for a demodulation, and the second signal path is arranged for amplification for determination of a power of the signal present. In the second operating state, one of the two signal paths is inactive and the other is arranged for demodulating the signal present.

Abstract: The invention discloses a signal conditioning circuit having a vector demodulator for breaking down a signal applied to the input into a first component and a second component. The outputs of the vector demodulator having at least one first amplifier circuit comprising a first and a second input connected thereto which may be configured to amplify signals applied to the input using an adjustable gain. The outputs of the at least one first amplifier circuit are connected to a first analog/digital converter. A polyphase filter may be connected between outputs of the vector demodulator and the input of the first amplifier circuit. The polyphase filter has an adjustable filter bandwidth.

Abstract: An amplifier arrangement contains a first signal input for supplying a carrier signal, a second signal input for supplying an amplitude modulation word and an amplifier stage. The amplifier stage is connected to a reference potential connection and, by means of a control connection via a means for DC signal suppression, to the first signal input. A DC voltage converter having a first connection for supplying a potential is designed to convert the potential into a supply potential, which is variable over a period of time, on the basis of a control signal, and outputs the supply potential to the second connection of the amplifier stage. In addition, the amplifier arrangement comprises a digital/analog converter which is coupled to the control connection of the amplifier stage. The input of the converter is connected to the second signal input.

Abstract: A phase-modulated signal (1) is divided into an in-phase component and a quadrature-phase component. The in-phase component is supplied to a first one-bit analogue/digital converter (25) and the quadrature-phase component is supplied to a second one-bit analogue/digital converter (26), output signals (8; 9) of the one-bit analogue/digital converters (26; 27) being evaluated for determining data modulated onto the phase-modulated signal (1). The one-bit analogue/digital converters may be constructed as simple comparators (26; 27).

Abstract: A sigma-delta converter has a signal input for receiving a data word. A clock signal input is designed to supply a clock signal. The sigma-delta converter includes a first clocked-operation accumulator stage whose input side is connected to the signal input, and at least one second clocked-operation accumulator stage connected in series with the first accumulator stage, with its input side coupled to an accumulator output of the first accumulator stage. The sigma-delta converter is configured to process the data word upon each clock signal only in one accumulator stage in the first and the at least one second accumulator stage, and output the processed data word at the accumulator output of the one accumulator stage. As a result, a time-critical response during signal processing is limited just to the accumulator stage which is currently processing the data word.

Abstract: An oscillator is disclosed that is tunable to discrete values, and includes a tuning element which can be connected via a switching device. A rectifier circuit is connected to the output of the oscillator and forms a clock signal from the oscillator signal. The oscillator circuit contains a phase delay circuit having a switching input, a clock signal input which is coupled to the output of the rectifier circuit, and a switching output coupled to the switching device. The phase delay circuit has a comparison circuit for comparison of a phase of the clock signal that is applied to the signal input with a reference phase. This phase delay circuit is designed to emit a switching signal after application of an activation signal to the switching input and after the phase of the clock signal which is applied to the signal input matches the reference phase.

Abstract: The invention is directed to a phase locked loop with a ?? modulator. A multimodulus divider in the feedback path of the PLL is actuated by the ?? modulator. The latter has a design which can be described by a complex transfer function H(s) in the Laplace plane, said transfer function having a complex-conjugate pair of pole points. The arrangement allows a significant reduction in the noise in critical frequency domains and hence allows adherence to transmission masks based on radio specification even when the PLL bandwidth is as large as the modulation bandwidth.

Abstract: The transmitting/receiving device has a polar modulator with a variable predistorter (11, 12) and an amplifier (8) which can be modulated, a reception path (25) which can be operated both during conventional reception and for the purposes of adjustment of the predistorter (11, 12) in order to determine a measurement signal (35) which is dependent on the output signal from the amplifier (8), and a coupling path for coupling of the reception path (25) to the output from the amplifier (8). A control and evaluation means (34, 36) is additionally provided for adjustment of the predistorter (11, 12).

Abstract: A polar modulator contains a phase locked loop which is designed to emit a radio-frequency signal at one frequency to one output, with the frequency being derived from the reference signal and from a phase modulation signal at a control input of the phase locked loop. The modulator additionally has a second signal input for supplying an amplitude modulation signal. The second signal input is connected to a control input of a pulse width modulator, one of whose signal inputs is coupled to the output of the phase locked loop. The pulse width modulator is designed to vary the duty ratio of a signal which is applied to the signal input, with this variation being adjustable via a regulation signal at the control input. A filter can be connected downstream from the output of the pulse width modulator and suppresses higher harmonic components in a signal which can be tapped off at the output of the pulse width modulator.

Abstract: A modulated carrier signal is produced from a phase modulation signal in a phase locked loop in a polar modulator. This carrier signal is converted via a limiting amplifier to a square-wave signal, which is supplied to an amplifier. At the same time, an amplitude modulation signal at one input is connected to a control input of a controllable current source. The controllable current source is designed to emit a supply current at a current output as a function of the amplitude modulation signal at the control input. The current output of the controllable current source is connected to a supply input of the amplifier. The supply current for the amplifier is thus modulated on the basis of the amplitude information to be transmitted. The processing of the amplitude information within the current domain makes it possible to produce the polar modulator according to the invention as an integrated circuit, using CMOS technology.

Abstract: A VCO circuit (20) has a coil (21) and, in parallel therewith, a constant capacitance (24) and adjustable capacitance elements (22, 23). A first capacitance element (22) is formed by one or more varactors whose capacitance can be adjusted by an analogue adjusting voltage (Vtune), while a second capacitance element (23) is formed by an arrangement comprising a plurality of capacitors which can be actuated by a digital bit word VCWD[N:1]. Digital calibration for the VCO (20) is performed by determining whether the present adjusting voltage is within a particular voltage range and, if this is not the case, the digital bit word being incremented or decremented by a bit value.

Abstract: A polar modulator has a low AM-AM and AM-PM distortion comprises a phase locked loop. The phase locked loop is designed for outputting a high-frequency signal with a frequency derived from a phase modulation signal at an actuating input of the phase locked loop. A filter device, for suppressing a DC signal component, is coupled to an output of the phase locked loop. Furthermore, provision is made of a controllable voltage source with a control input suitable for feeding in an amplitude modulation signal. A push-pull amplifier is connected by an input to the filter device. It comprises two feedback amplifier transistors connected in series, which are connected to a voltage output of the controllable voltage source for supply purposes. Control terminals of the amplifier transistors are connected to the input and, via a load, to an output of the push-pull amplifier.

Abstract: The present invention relates to a receiving apparatus for a mobile communications system which can be modulated using different modulation types at the transmitter end. According to one embodiment of the invention, in the middle of a data burst of a Bluetooth communications system, a GFSK modulation method is switched to an M-DPSK modulation method, which is used for the payload data. A frequency offset estimation unit is provided for GFSK-modulated signals in a first receiving section and estimates the frequency offset by averaging over a bit sequence of a trailer of a data burst. The frequency offset is corrected in a second receiving section, by means of a frequency correction unit which operates on the basis of the CORDIC algorithm.

Abstract: The invention relates to a radio receiver for the reception of a data burst which is transmitted by a transmitter, in which case the data burst includes a first section which has been modulated using a first modulation method at the transmitter end, and a second section which is transmitted after the first section and has been modulated using a second modulation method at the transmitter end. The radio receiver has a first reception path for processing of the first section and a second reception path for processing of the second section.

Abstract: The modulator according to the invention is based on the modulation of a PLL, with the bandwidth of the PLL being variable. The modulator also has a means (14, 15) for determination of a signal (?r(kTs); FDEV) which is characteristic of the modulation shift of the modulated signal.

Abstract: The mobile radio receiver comprises a variable amplifier (3), a first means (9, 10) for comparison of a signal, which is characteristic of the amplitude of a received signal, with at least one analogue comparison value (PDTHR), a second means (13, 14, 17) for comparison of a signal, which is characteristic of the amplitude of a received signal, with at least one digital comparison value (RSSITHR), and a third means (17, 11) for setting the gain, which is driven by the first means (9, 10) and by the second means (13, 14, 17).

Abstract: The invention is directed to a phase locked loop with a ?? modulator. A multimodulus divider in the feedback path of the PLL is actuated by the ?? modulator. The latter has a design which can be described by a complex transfer function H(s) in the Laplace plane, said transfer function having a complex-conjugate pair of pole points. The arrangement allows a significant reduction in the noise in critical frequency domains and hence allows adherence to transmission masks based on radio specification even when the PLL bandwidth is as large as the modulation bandwidth.

Abstract: The invention provides a phase locked loop having a modulator which is based on a ?? fractional N phase locked loop. In the forward path of the PLL, the output of the oscillator has an additional frequency divider which provides the output frequency of the PLL in a plurality of different phases. A multiplexer which is connected upstream of the multimodulus divider in the PLL's feedback path and which is actuated by the ?? modulator, like the divider, selects the respective desired phase. This allows the minimum step size of the division factors to be reduced to values of less than 1 relative to the output frequency, which significantly reduces the quantization noise. The PLL bandwidth may therefore advantageously be the same size as the modulation bandwidth.

Abstract: A receiving arrangement for a cordless communication system includes an analog radio-frequency input section and a digital signal processing device connected downstream thereof. The digital signal processing device has an analog/digital converter which is followed by a digital mixing stage and a decimation unit. The decimation factor of the decimation unit is switchable in order to achieve an advantageous implementation for various systems.

Abstract: The phase locked loop according to the invention has an adjustable charge pump (2) which is intended to generate a control voltage (UVCO). A voltage-controlled oscillator (4) and an evaluation unit (14) are connected downstream of said charge pump. In this case, the evaluation unit (14) is designed in such a manner that it can be used to generate a correction signal (Iref) using the control voltage (UVCO) and a nominal gradient ({circumflex over (K)} vco) of the voltage-controlled oscillator (4) and to apply said signal to the evaluation output. The latter is, in turn, connected to an input of the charge pump (2).