Abstract: An interconnect system adapted for acting as a data path for transferring data fields on a bus between a plurality of initiators and targets operates in such a way that each data field is transferred during a respective cycle of a corresponding clock signal. The system is configured in such a way that the said data fields are divided into a first and a second part. Similarly, the cycle of the clock signal is divided into a first and a second part. The first and the second part of each data field are transferred, respectively, during the first and the second part of the cycle of the clock signal. Data fields having a size of 128 bits, for example, can thus be transferred on a 64-bit data path structure without any negative effect on the system performance and without the necessity of increasing the clock frequency; this facilitates the integration of the system on a chip.