Patents by Inventor Giuseppe Sciascia

Giuseppe Sciascia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Row address decoding block for non-volatile memories and methods for decoding pre-decoded address information
    Patent number: 9275708
    Abstract: Decoding blocks, memories, and methods for decoding pre-decoded address information are disclosed. One such decoding block includes a first latch and voltage shift circuit configured to receive first pre-decoded address information at first voltage levels and further configured to latch the first pre-decoded address information and shift the voltage levels of the same to second voltage levels. An address decoder includes a second latch and voltage shift circuit configured to receive second pre-decoded address information at the first voltage levels and latch and shift the voltage levels of the same to the second voltage levels. The address decoder is further configured to select control gates of the memory cells of the memory based at least in part on the first and second pre-decoded address information.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: March 1, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Marco Giovanni Fontana, Giuseppe Sciascia, Giovanni Bolognini
  • ROW ADDRESS DECODING BLOCK FOR NON-VOLATILE MEMORIES AND METHODS FOR DECODING PRE-DECODED ADDRESS INFORMATION
    Publication number: 20140160875
    Abstract: Decoding blocks, memories, and methods for decoding pre-decoded address information are disclosed. One such decoding block includes a first latch and voltage shift circuit configured to receive first pre-decoded address information at first voltage levels and further configured to latch the first pre-decoded address information and shift the voltage levels of the same to second voltage levels. An address decoder includes a second latch and voltage shift circuit configured to receive second pre-decoded address information at the first voltage levels and latch and shift the voltage levels of the same to the second voltage levels. The address decoder is further configured to select control gates of the memory cells of the memory based at least in part on the first and second pre-decoded address information.
    Type: Application
    Filed: February 13, 2014
    Publication date: June 12, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Marco Giovanni Fontana, Giuseppe Sciascia, Giovanni Bolognini
  • Row address decoding block for non-volatile memories and methods for decoding pre-decoded address information
    Patent number: 8681572
    Abstract: Decoding blocks, memories, and methods for decoding pre-decoded address information are disclosed. One such decoding block includes a first latch and voltage shift circuit configured to receive first pre-decoded address information at first voltage levels and further configured to latch the first pre-decoded address information and shift the voltage levels of the same to second voltage levels. An address decoder includes a second latch and voltage shift circuit configured to receive second pre-decoded address information at the first voltage levels and latch and shift the voltage levels of the same to the second voltage levels. The address decoder is further configured to select control gates of the memory cells of the memory based at least in part on the first and second pre-decoded address information.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: March 25, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Marco Giovanni Fontana, Giuseppe Sciascia, Giovanni Bolognini
  • ROW ADDRESS DECODING BLOCK FOR NON-VOLATILE MEMORIES AND METHODS FOR DECODING PRE-DECODED ADDRESS INFORMATION
    Publication number: 20120243344
    Abstract: Decoding blocks, memories, and methods for decoding pre-decoded address information are disclosed. One such decoding block includes a first latch and voltage shift circuit configured to receive first pre-decoded address information at first voltage levels and further configured to latch the first pre-decoded address information and shift the voltage levels of the same to second voltage levels. An address decoder includes a second latch and voltage shift circuit configured to receive second pre-decoded address information at the first voltage levels and latch and shift the voltage levels of the same to the second voltage levels. The address decoder is further configured to select control gates of the memory cells of the memory based at least in part on the first and second pre-decoded address information.
    Type: Application
    Filed: March 24, 2011
    Publication date: September 27, 2012
    Inventors: Marco Giovanni Fontana, Giuseppe Sciascia, Giovanni Bolognini