Abstract: Systems and methods are described for transmitting data over physical channels to provide a high bandwidth, low latency interface between integrated circuit chips with low power utilization. Communication is performed using group signaling over multiple wires using a vector signaling code, where each wire carries a low-swing signal that may take on more than two signal values.

Abstract: Systems and methods are described for transmitting data over physical channels to provide a high bandwidth, low latency interface between integrated circuit chips with low power utilization. Communication is performed using group signaling over multiple wires using a vector signaling code, where each wire carries a low-swing signal that may take on more than two signal values.

Abstract: Systems and methods are described for transmitting data over physical channels to provide a high bandwidth, low latency interface between integrated circuit chips with low power utilization. Communication is performed using group signaling over multiple wires using a vector signaling code, where each wire carries a low-swing signal that may take on more than two signal values.

Abstract: Systems and methods are described for transmitting data over physical channels to provide a high bandwidth, low latency interface between integrated circuit chips with low power utilization. Communication is performed using group signaling over multiple wires using a vector signaling code, where each wire carries a low-swing signal that may take on more than two signal values.

Abstract: Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices with significantly reduced or eliminated Simultaneous Switching Output noise. Controller-side and memory-side embodiments of such channel interfaces are disclosed which do not require additional pin count or data transfer cycles, have low power utilization, and introduce minimal additional latency. In some embodiments of the invention, three or more voltage levels are used for signaling.

Abstract: A data receiver has a clock recovery and data sampling circuit. This has a fixed local oscillator for timing the data samples. A phase interpolator adjusts the phase of the clock signal in response to an early late detector which samples the waveform at the expected position of the edges. A further correction to the sampling position is made in response to the recent history of the data received. The correction is modelled on predictable jitter, for example, that in a transmitter caused by changes in data causing the supply voltage to drop.

Abstract: A data receiver has a clock recovery and data sampling circuit. This has a fixed local oscillator for timing the data samples. A phase interpolator adjusts the phase of the clock signal in response to an early late detector which samples the waveform at the expected position of the edges. A further correction to the sampling position is made in response to the recent history of the data received. The correction is modelled on predictable jitter, for example, that in a transmitter caused by changes in data causing the supply voltage to drop.

Abstract: In an integrated circuit receiving multiple serial data streams in parallel, a local clock is generated from each data stream and is synchronized with the data stream. Sometimes a data stream may have no transitions making it difficult to keep the clock synchronized with its data. A clock channel is provided, which always has edges. A circuit is provided for each data stream which measures the time elapsed since the data stream had an edge. After a certain period, the phase of the local clock is nudged towards that of the clock channel. Thereafter, the longer there are no edges on the data stream the more frequently nudges towards the phase of the clock channel are made.

Abstract: A digital system aligns a set of serial data receiver demultiplex circuits, thereby aligning the bits in the data words, while maintaining separate and optimally aligned data recovery clocks for each channel. The digital system generates a reference clock signal and one or more slave clock signals. Phase circuitry receives the slave clock signal and outputs a plurality of clock phase signals. A phase selection circuit receives the plurality of clock phase signals and selects an adjusted clock signal in response to a phase selection signal. A clock correlation circuit determines a phase difference between the reference clock signal and the adjusted clock signal and provides the phase selection signal to minimize the phase difference. The clock correlation circuit provides the phase selection signal from a counter.

Abstract: In an integrated circuit receiving multiple serial data streams in parallel, a local clock is generated from each data stream and is synchronised with the data stream. Sometimes a data stream may have no transitions making it difficult to keep the clock synchronised with its data. A clock channel is provided, which always has edges. A circuit is provided for each data stream which measures the time elapsed since the data stream had an edge. After a certain period, the phase of the local clock is nudged towards that of the clock channel. Thereafter, the longer there are no edges on the data stream the more frequently nudges towards the phase of the clock channel are made.

Abstract: A digital system is provided with a means for achieving alignment between a set of serial data receiver demultiplex circuits, thereby achieving alignment of the bits in the data words, while maintaining the use of separate and therefore optimally aligned data recovery clocks for each channel signal. The digital system is provided with circuitry for generating a reference clock signal and clock circuitry for generating one or more slave clock signals. Phase circuitry is connected to receive the slave clock signal and has outputs for providing a plurality of clock phase signals. A phase selection circuit is connected to receive the plurality of clock phase signals. The phase selection circuit has an output for providing an adjusted clock signal selected from the plurality of clock phase signals in response to a phase selection signal.

Abstract: Parallel transmitted data in a plurality of channels is synchronised by generating a clock on the basis of the received data and synchronising the data received on each channel with the generated clock signal (50).

Abstract: A symmetrical loading and current supply arrangement is described for a differential-type logic means, and symmetrical voltage swings are thereby achieved in the logic output. In a preferred arrangement the output voltages are self-aligned to a CMOS level which facilitate conversion of the differential-type output to CMOS signals.