Patents by Inventor Giuseppe Valbonesi

Giuseppe Valbonesi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4081611
    Abstract: A coupling network at the junction of several multichannel TDM/PCM links comprises a pair of switching networks each including a set of input group units receiving incoming messages from respective PCM links, a set of output group units transmitting outgoing messages to respective PCM links, and a switching matrix interconnecting the two sets of group units. The bits of a code word representing an incoming message sample, arriving at a line unit individually associated with the respective PCM channel, are delivered to the corresponding input group unit during a receiving period, are read out during a transfer interval via the switching matrix to the output group unit for which they are intended, and are thence fed to the proper line unit during a transmitting period.
    Type: Grant
    Filed: April 13, 1976
    Date of Patent: March 28, 1978
    Assignee: Societa Italiana Telecomunicazioni SIEMENS S.p.A.
    Inventors: Amilcare Bovo, Giampaolo Gubertini, Luigi Musumeci, Giuseppe Valbonesi
  • Patent number: 3938086
    Abstract: A receiver of n-bit data words, each consisting of k information bits and (n-1) redundancy bits, comprises three error detectors receiving the incoming bit stream in parallel with one another and with a shift register of a transfer circuit, the three error detectors being triggered by timing pulses fed to them in staggered relationship from a clock circuit extracting synchronizing signals from the bit stream. In normal operation, the middle detector generates a recurrent no-error output signal which has no effect upon the cadence of the timing pulses. If either of the two other detectors emits such a no-error output signal in response to a forward or a backward slip by a predetermined number of bits h, the clock circuit is reset to compensate for the slip. The emission of an output signal from any error detector causes the readout of the received bits from the shift register in the transfer circuit.
    Type: Grant
    Filed: April 11, 1975
    Date of Patent: February 10, 1976
    Assignee: Societa Italiana Telecomunicazioni Siemens S.p.A.
    Inventor: Giuseppe Valbonesi