Patents by Inventor Giuseppe Vito Portacci

Giuseppe Vito Portacci has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240061748
    Abstract: Methods, systems, and devices for memory recovery partitions are described. A memory system may include a memory array configured with one or more logical partitions. In some examples, a primary boot image may be stored to a first logical partition and a recovery boot image may be stored to a second logical partition. During a boot operation, the memory system may determine whether the primary boot image includes one or more errors. If the primary boot image includes relatively few (or no) errors, the memory system may boot using the primary boot image. If the primary boot image includes a relatively high quantity of errors (e.g., higher than a threshold quantity of errors), the memory system may autonomously load a recovery boot image stored to the second logical partition.
    Type: Application
    Filed: July 13, 2023
    Publication date: February 22, 2024
    Inventors: Lance W. Dover, Giuseppe Vito Portacci, Giuseppe Ferrari
  • Patent number: 11657878
    Abstract: Methods, systems, and devices for initialization techniques for memory devices are described. A memory system may include a memory array on a first die and a controller on a second die, where the second die is coupled with the first die. The controller may perform an initialization procedure based on operating instructions stored within the memory system. For example, the controller may read a first set of operating instructions from read-only memory on the second die. The controller may obtain a second set of operating instructions stored at a memory block of the memory array on the first die, with the memory block indicated by the first set of operating instructions. The controller may complete or at least further the initialization procedure based on the second set of operating instructions.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: May 23, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Antonino Pollio, Giuseppe Vito Portacci, Mauro Luigi Sali, Alessandro Magnavacca
  • Publication number: 20230129539
    Abstract: Methods, systems, and devices for authenticated modification of memory system data are described. A host system may transmit a command to program data to a protection region of a memory system, and the host system may sign the command using a key associated with the protection region. In some examples, the host system may transmit the data associated with the command, or the command may include instructions to move the data from another region of the memory system. Upon receiving the command, the memory system may verify the signature to determine whether the host is authorized to modify the protection region, and may program the data as requested by the host system. In some cases, the protection regions of the memory system may be updated, for example by adjusting the size or address range of the protection regions, in response to a command from the host system.
    Type: Application
    Filed: May 20, 2022
    Publication date: April 27, 2023
    Inventors: Lance W. Dover, Giuseppe Vito Portacci, Giuseppe Ferrari
  • Publication number: 20230126605
    Abstract: Methods, systems, and devices for authenticated reading of memory system data are described. In some examples, a host system and a memory system may exchange keys used to grant the host system access to one or more protected regions of the memory system. The keys may be symmetric or asymmetric. In some cases, the host system may transmit a read command to access data stored at a protected region of the memory system, along with a signature generated using the key associated with the protected region. The memory system may verify the signature to determine whether the host is authorized to access the protected region, and may transmit the requested data to the host system. In some examples, the memory system may sign the returned data, so that the host system may verify the source of the data.
    Type: Application
    Filed: May 20, 2022
    Publication date: April 27, 2023
    Inventors: Lance W. Dover, Giuseppe Vito Portacci, Giuseppe Ferrari
  • Publication number: 20220223211
    Abstract: Methods, systems, and devices for initialization techniques for memory devices are described. A memory system may include a memory array on a first die and a controller on a second die, where the second die is coupled with the first die. The controller may perform an initialization procedure based on operating instructions stored within the memory system. For example, the controller may read a first set of operating instructions from read-only memory on the second die. The controller may obtain a second set of operating instructions stored at a memory block of the memory array on the first die, with the memory block indicated by the first set of operating instructions. The controller may complete or at least further the initialization procedure based on the second set of operating instructions.
    Type: Application
    Filed: January 27, 2022
    Publication date: July 14, 2022
    Inventors: Antonino Pollio, Giuseppe Vito Portacci, Mauro Luigi Sali, Alessandro Magnavacca
  • Patent number: 11238940
    Abstract: Methods, systems, and devices for initialization techniques for memory devices are described. A memory system may include a memory array on a first die and a controller on a second die, where the second die is coupled with the first die. The controller may perform an initialization procedure based on operating instructions stored within the memory system. For example, the controller may read a first set of operating instructions from read-only memory on the second die. The controller may obtain a second set of operating instructions stored at a memory block of the memory array on the first die, with the memory block indicated by the first set of operating instructions. The controller may complete or at least further the initialization procedure based on the second set of operating instructions.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: February 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Antonino Pollio, Giuseppe Vito Portacci, Mauro Luigi Sali, Alessandro Magnavacca
  • Patent number: 6172901
    Abstract: Described is an SRAM cell made from two cross-coupled inverters. The output from each inverter is a data node, and the two data nodes store logical complementary signals. Each data node is connected to a pass transistor that is coupled directly to the power supply voltage, rather than coupled to a pair of bitlines. The inverters can be connected to a reading circuit, a writing circuit, or a stand-by circuit as desired for different phases of the memory operation. Data is read from the SRAM cell by using a current sensing differential amplifier. Data is written to the SRAM cell by controlling voltages on the cross-coupled inverters, and compatible with conventional writing signals.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: January 9, 2001
    Assignee: STMicroelectronics, S.r.l.
    Inventor: Giuseppe Vito Portacci