Abstract: A requesting processor issues an instruction containing a segmented virtual space identifier (VSID) and a shared-access or nonshared-access identifier. A single translation lookaside buffer is divided into TLB partitions which have corresponding directory registers. Each directory register has a first field for storing a VSID and a second field have bit positions respectively assigned to the processors of the system. If the instruction contains a nonshared-access identifier, a directory controller selects one of the registers whose second field contains all vacant bit positions and writes the VSID of the instruction into the register and sets a bit in a position assigned to the requesting processor. The controller detects a register having the same VSID and first and second bits in positions respectively assigned to the master and requesting processors, and resets the second bit.

Abstract: In a memory access control device (10) for use in controlling access by at least one address signal to a memory device (11) comprising memory modules each of which comprises a plurality of memory banks, a module checking circuit (16) checks first and second module signals indicative of the memory modules to produce a module coincidence signal when the first and the second module signals coincide with each other. First and second bank access checking circuits (17, 18) are assigned with first and second preselected number of memory modules and check first and second bank address signals indicative of the memory banks and first and second bank access held signals indicative of at least two of the memory banks which should be accessed. The first and the second bank access checking circuits produce first and second bank coincidence signals when the first and the second bank address signals coincide with the first and the second bank access held signals.

Abstract: In a circuit arrangement for use in accessing selected address numbered with a preselected distance left between two adjacent ones of the selected addresses, a control circuit centralizes control operation of a switching network with reference to a reference one of the selected addresses and the preselected distance to make the switching network form internal paths between input and output port sets of the switching network. Alternatively, when ports of a selected one of the input and output port sets are accessed at a predetermined port interval, the control circuit controls the switching network with reference to the predetermined port interval and a reference port selected from the selected port set. A leading port of the other set is determined to be connected to the reference port. A rearranging circuit may be connected to one of the input and output port sets to rearrange an order of the ports of the one port set in consideration of the port distance.