Abstract: Subject matter disclosed herein may relate to correlated electron switch devices, and may relate more particularly to voltage detection with correlated electron switch devices.

Abstract: A high-speed memory circuit architecture for arrays of resistive change elements is disclosed. An array of resistive change elements is organized into rows and columns, with each column serviced by a word line and each row serviced by two bit lines. Each row of resistive change elements includes a pair of reference elements and a sense amplifier. The reference elements are resistive components with electrical resistance values between the resistance corresponding to a SET condition and the resistance corresponding to a RESET condition within the resistive change elements being used in the array. A high speed READ operation is performed by discharging one of a row's bit lines through a resistive change element selected by a word line and simultaneously discharging the other of the row's bit lines through of the reference elements and comparing the rate of discharge on the two lines using the row's sense amplifier. Storage state data are transmitted to an output data bus as high speed synchronized data pulses.

Abstract: A high-speed memory circuit architecture for arrays of resistive change elements is disclosed. An array of resistive change elements is organized into rows and columns, with each column serviced by a word line and each row serviced by two bit lines. Each row of resistive change elements includes a pair of reference elements and a sense amplifier. The reference elements are resistive components with electrical resistance values between the resistance corresponding to a SET condition and the resistance corresponding to a RESET condition within the resistive change elements being used in the array. A high speed READ operation is performed by discharging one of a row's bit lines through a resistive change element selected by a word line and simultaneously discharging the other of the row's bit lines through of the reference elements and comparing the rate of discharge on the two lines using the row's sense amplifier. Storage state data are transmitted to an output data bus as high speed synchronized data pulses.

Abstract: A high-speed memory circuit architecture for arrays of resistive change elements is disclosed. An array of resistive change elements is organized into rows and columns, with each column serviced by a word line and each row serviced by two bit lines. Each row of resistive change elements includes a pair of reference elements and a sense amplifier. The reference elements are resistive components with electrical resistance values between the resistance corresponding to a SET condition and the resistance corresponding to a RESET condition within the resistive change elements being used in the array. A high speed READ operation is performed by discharging one of a row's bit lines through a resistive change element selected by a word line and simultaneously discharging the other of the row's bit lines through of the reference elements and comparing the rate of discharge on the two lines using the row's sense amplifier. Storage state data are transmitted to an output data bus as high speed synchronized data pulses.

Abstract: A high-speed memory circuit architecture for arrays of resistive change elements is disclosed. An array of resistive change elements is organized into rows and columns, with each column serviced by a word line and each row serviced by two bit lines. Each row of resistive change elements includes a pair of reference elements and a sense amplifier. The reference elements are resistive components with electrical resistance values between the resistance corresponding to a SET condition and the resistance corresponding to a RESET condition within the resistive change elements being used in the array. A high speed READ operation is performed by discharging one of a row's bit lines through a resistive change element selected by a word line and simultaneously discharging the other of the row's bit lines through of the reference elements and comparing the rate of discharge on the two lines using the row's sense amplifier. Storage state data are transmitted to an output data bus as high speed synchronized data pulses.

Abstract: A dynamic sense current supply circuit and an associated method for rapidly characterizing a resistive memory array is disclosed. In one embodiment, the disclosed circuit comprises a first and second dynamically programmable current mirror sub-circuit. Responsive to a bank of control signals, each dynamically programmable current mirror sub-circuit provides a dynamically adjustable current scaling factor. These scaling factors are used to scale a supplied reference current to generate a plurality of sense currents which can be used within a plurality of read operations on a resistive memory array. A digital circuit is also provided to sense and store the result of each read operation.

Abstract: A dynamic sense current supply circuit and an associated method for rapidly characterizing a resistive memory array is disclosed. In one embodiment, the disclosed circuit comprises a first and second dynamically programmable current mirror sub-circuit. Responsive to a bank of control signals, each dynamically programmable current mirror sub-circuit provides a dynamically adjustable current scaling factor. These scaling factors are used to scale a supplied reference current to generate a plurality of sense currents which can be used within a plurality of read operations on a resistive memory array. A digital circuit is also provided to sense and store the result of each read operation.

Abstract: One-time programmable (OTP) nonvolatile fuse memory cells are disclosed that do not require decoding or addressing for reading their data content. Each fuse memory cell has its content latched at its output and available at all times and can be used, for example, for code storage memories, serial configuration memories, and as individual fuse bits for ID (identification), trimming, and other post-fabrication System-on-Chip (SoC) customization needs. Means are also provided for temporary data storage for design testing, etc. In alternative embodiments, using two differentially programmed fuses in a single memory cell, the selection and programming circuitry are merged.

Abstract: One-time programmable (OTP) nonvolatile fuse memory cells are disclosed that do not require decoding or addressing for reading their data content. Each fuse memory cell has its content latched at its output and available at all times and can be used, for example, for code storage memories, serial configuration memories, and as individual fuse bits for ID (identification), trimming, and other post-fabrication System-on-Chip (SoC) customization needs. Means are also provided for temporary data storage for design testing, etc. In alternative embodiments, using two differentially programmed fuses in a single memory cell, the selection and programming circuitry are merged.

Abstract: One-time programmable (OTP) nonvolatile fuse memory cells are disclosed that do not require decoding or addressing for reading their data content. Each fuse memory cell has its content latched at its output and available at all times and can be used, for example, for code storage memories, serial configuration memories, and as individual fuse bits for ID (identification), trimming, and other post-fabrication System-on-Chip (SoC) customization needs. Means are also provided for temporary data storage for design testing, etc. In alternative embodiments, using two differentially programmed fuses in a single memory cell, the selection and programming circuitry are merged.

Abstract: A circuit for transferring high voltage analog video signals while enabling the use of conventional low voltage logic levels includes a first transistor powered by a high voltage power source to bias a pass transistor at a high voltage level. The pass transistor receives a high voltage video signal and because of the high voltage bias is able to pass the video signal without attenuation of the signal due to feedthrough effects, thus preserving the fidelity of the video signal. A second transistor provides a ground potential which operates to turn OFF the pass transistor, thus disabling the transfer of the video signal therethrough. A third transistor operatively coupled to the first transistor operates to turn OFF the first transistor when the second transistor is in operation.

Abstract: A video chip includes test circuitry for detecting opens and shorts. The circuitry includes a series-connected chain of transistors and a test register. There is a circuit for the column lines and for the row lines. A bit pattern is driven onto the column or the row lines and received in the corresponding test circuitry. The pattern is read out and compared against the input pattern to detect faulty lines.

Abstract: A sense amplifier for use in a serial configuration memory includes multiple stages which are enabled and disabled in a controller manner, in response to a control pulse. The control pulse is produced every Nth period of an externally provided clock signal, the clock being used to clock out a bitstream representing the contents of the memory device. In a preferred embodiment, N such sense amps are utilized to read out in parallel fashion the N memory cells (bits) that constitute an accessed memory location. The sense amps are therefore active only of a period of time sufficient to read out a memory cell.

Abstract: A serial configuration memory device comprises an architecture wherein the reading out of data and the outputting of the bitstream are performed in pipeline fashion. As a result, the device is capable of outputting a bitstream based solely on the frequency of an externally provided clock, and is not limited by the slower operating speed of the sense amp circuitry. A caching scheme is provided which allows the first byte to be pre-loaded during a reset cycle so that the device can immediately begin outputting the bitstream as soon as the reset cycle completes. In a preferred embodiment of the invention, the bitstream consists of serially accessed memory locations starting from memory location zero. In one variation, the bitstream can begin from a memory location other than memory location zero.

Abstract: A power-on-reset circuit includes a first charging stage for building up a charge during power up. The rising voltage of the first charging stage is sensed and used to control means for charging up a second charging stage. When the second charging stage reaches a first voltage level, a circuit is tripped to pull the potential of the first to ground. The grounding of the first charging stage is fed back to the charging means which shuts off its power burning components and maintains the first voltage level at the second charging stage.

Abstract: A high voltage circuit includes a first switching device for supplying one of a high voltage (V.sub.pp) and a low voltage (V.sub.cc) to a controlled path that includes a series connection of a control p-channel transistor and a protection p-channel transistor. A high voltage detector is utilized to determine whether V.sub.pp or V.sub.cc is applied to the controlled path. The high voltage detector also establishes a protecting condition for the protection p-channel transistor during V.sub.pp operation. On the other hand, the detector establishes a non-protecting condition during V.sub.cc operation, thereby rendering the protecting p-channel transistor transparent to circuit performance. A signal input switches the control p-channel transistor between on and off states.

Abstract: A protection circuit includes a first controlled path for discharging negative ESD pulses introduced at a signal node. The first controlled path is from the signal node to V.sub.cc via the source and drain electrodes of a first transistor. The gate of the transistor is at a soft ground by connection of the gate through a resistor and an inverter to a fixed voltage supply potential (V.sub.cc). A second controlled path discharges positive ESD pulses via source and drain regions of serially connected second and third transistors to ground. The second transistor has a gate tied at V.sub.cc by means of a resistor and inverter to ground. The third transistor is at soft ground by means of a resistor and inverter to V.sub.cc. The third transistor is turned on by a positive voltage exceeding the threshold voltage of the third transistor, but the second transistor prevents damage to the third transistor by limiting the voltage applied to the third transistor.

Abstract: A method is provided for testing a non-programmable non-volatile memory which does not require the writing or erasing of any cells and permits the testing of all normal memory cells. Testing occurs from the device I/O pins and is useful in cases where EPROM memory cells have been bulk erased and placed within an ultraviolet-opaque package. The non-volatile memory is of the type having memory banks of rows and columns. Each bank must have address decoders and means for changing addresses between banks. A separate auxiliary cell or row of cells in a state different from the non-programmed state is provided. An address is supplied for the auxiliary cells and then for the normal cells and the interval between addressing the normal cells and the appearance of an output signal is measured and compared with a predetermined fixed limit. If the limit is exceeded, the address is identified as that of a weak cell whose speed does not meet product specifications.

Abstract: A read circuit for a semiconductor memory that includes a pass transistor between the output of a first sense amplifier reading the memory and a latch. The pass transistor blocks transmission of the sense amplifier's output to the latch whenever a noise glitch producing condition is sensed. A second sense amplifier connected through the same conductive line to the memory cell array as the first sense amplifier has a faster response and lower current threshold in order to detect the glitch producing condition. A pulse generator receives the output of the second sense amplifier and provides a control signal pulse of predetermined duration following detection of the glitch producing condition by the second sense amplifier. The pulse is received by a control gate of the pass transistor, turning the transistor off during the duration of the pulse.