Abstract: A multi-mode control device is provided for controlling an external load device. The control device includes a high-power interface, a low-power interface, and a control module. The high-power interface can be electrically coupled to a high-power module providing current from an external power source to the load device. The low-power interface can be electrically coupled to a low-power module. The high-power interface can receive a first current from the high-power module. The low-power interface can receive a second current from the low-power module that is less than the first current. The low-power interface can prevent the first current from flowing to the low-power module. The control module, which is electrically coupled to the high-power interface and the low-power interface, be powered by one or more of the first and second current.

Abstract: A multi-mode control device is provided for controlling an external load device. The control device includes a high-power interface, a low-power interface, and a control module. The high-power interface can be electrically coupled to a high-power module providing current from an external power source to the load device. The low-power interface can be electrically coupled to a low-power module. The high-power interface can receive a first current from the high-power module. The low-power interface can receive a second current from the low-power module that is less than the first current. The low-power interface can prevent the first current from flowing to the low-power module. The control module, which is electrically coupled to the high-power interface and the low-power interface, can operate in a high-power mode for powering the control module using the first current and a low-power mode for powering the control module using the lower second current.

Abstract: A multi-mode control device is provided for controlling a load device. A high-power interface of the control device can be electrically coupled to a high-power module. An occupancy sensor can receive a first current from the high-power module via the high-power interface, and a trigger detection device can receive a second current that is less than the first current from a low-power module via a low-power interface. The processor can switch the control device from a high-power mode for powering the occupancy sensor to a low-power mode by causing a reduction in the current provided to the occupancy sensor and causing current to be provided to the trigger detection device. The trigger detection device can detect a trigger in the low-power mode. The processor can cause the control device to operate in the high-power mode based on the trigger's detection.

Abstract: A multi-mode control device is provided for controlling a load device. A high-power interface of the control device can be electrically coupled to a high-power module. An occupancy sensor can receive a first current from the high-power module via the high-power interface, and a trigger detection device can receive a second current that is less than the first current from a low-power module via a low-power interface. The processor can switch the control device from a high-power mode for powering the occupancy sensor to a low-power mode by causing a reduction in the current provided to the occupancy sensor and causing current to be provided to the trigger detection device. The trigger detection device can detect a trigger in the low-power mode. The processor can cause the control device to operate in the high-power mode based on the trigger's detection.

Abstract: A multi-mode control device is provided for controlling a load device. A high-power interface of the control device can be electrically coupled to a high-power module for providing current to the load device. An occupancy sensor can receive a first current from the high-power module via the high-power interface, and a trigger detection device can receive a second current that is less than the first current from a low-power module via a low-power interface. The processor can switch the control device from a high-power mode for powering the occupancy sensor to a low-power mode by causing a reduction in the current provided to the occupancy sensor and causing current to be provided to the trigger detection device. The trigger detection device can detect a trigger in the low-power mode. The processor can cause the control device to operate in the high-power mode based on the trigger's detection.

Abstract: Retrofit light fixtures suitable for installation without tools. One or more spring bands deform as the fixture is forced through a ceiling opening and resume their preloaded shape to hold the fixture in place. Some embodiments may be installed in round ceiling openings and may utilize LED light sources.

Abstract: An out-of-order processor 4 groups program instructions together to control their commitment to complete processing. If an instruction within a group has a source operand dependent upon a plurality of destination operands of other instructions then this is identified as a size mismatch hazard. When the program instruction having the size mismatch hazard reaches a commit point within the processor, then it is flushed together with any speculatively executed succeeding program instructions. Furthermore, the group of program instructions containing the program instruction containing the program instruction having the size mismatch is divided into a plurality of groups of program instructions each containing a single program instruction which are then replayed through the processing mechanisms.

Abstract: A multi-mode control device is provided for controlling an external load device. The control device includes a high-power interface, a low-power interface, and a control module. The high-power interface can be electrically coupled to a high-power module providing current from an external power source to the load device. The low-power interface can be electrically coupled to a low-power module. The high-power interface can receive a first current from the high-power module. The low-power interface can receive a second current from the low-power module that is less than the first current. The low-power interface can prevent the first current from flowing to the low-power module. The control module, which is electrically coupled to the high-power interface and the low-power interface, can operate in a high-power mode for powering the control module using the first current and a low-power mode for powering the control module using the lower second current.

Abstract: A multi-mode control device is provided for controlling a load device. A high-power interface of the control device can be electrically coupled to a high-power module for providing current to the load device. An occupancy sensor can receive a first current from the high-power module via the high-power interface, and a trigger detection device can receive a second current that is less than the first current from a low-power module via a low-power interface. The processor can switch the control device from a high-power mode for powering the occupancy sensor to a low-power mode by causing a reduction in the current provided to the occupancy sensor and causing current to be provided to the trigger detection device. The trigger detection device can detect a trigger in the low-power mode. The processor can cause the control device to operate in the high-power mode based on the trigger's detection.

Abstract: A processor core supports execution of program instruction from both a first instruction set and a second instruction set. An architectural register file 18 containing architectural registers is shared by the two instruction sets. The two instruction sets employ logical register specifiers which for at least some values of those logical registers specifiers correspond to different architectural registers within the architectural register file 18. A first decoder 4 for the first instruction set and a second decoder 6 for the second instruction set serve to decode the logical register specifiers to a common register addressing format. This common register addressing format is used to supply register specifiers to renaming circuitry 10 for supporting register renaming in conjunction with a physical register file 16 and an architectural register file 18.

Abstract: A data processing system is provided in which destination operands to be stored within architectural registers are constrained to have zero values added as prefixes in order that the architectural register value has a fixed bit width irrespective of the bit width of the destination operand being written thereto. Instead of adding these zero values everywhere in the data path, they are instead represented by zero flags in at least the physical registers utilized for register renaming operations and in the result queue prior to results being written to the architectural register file. This saves circuitry resources and reduces energy consumption.

Abstract: A processor core supports execution of program instruction from both a first instruction set and a second instruction set. An architectural register file 18 containing architectural registers is shared by the two instruction sets. The two instruction sets employ logical register specifiers which for at least some values of those logical registers specifiers correspond to different architectural registers within the architectural register file 18. A first decoder 4 for the first instruction set and a second decoder 6 for the second instruction set serve to decode the logical register specifiers to a common register addressing format. This common register addressing format is used to supply register specifiers to renaming circuitry 10 for supporting register renaming in conjunction with a physical register file 16 and an architectural register file 18.

Abstract: Retrofit light fixtures suitable for installation without tools. One or more spring bands deform as the fixture is forced through a ceiling opening and resume their preloaded shape to hold the fixture in place. Some embodiments may be installed in round ceiling openings and may utilize LED light sources.

Abstract: A data processing system is provided in which destination operands to be stored within architectural registers are constrained to have zero values added as prefixes in order that the architectural register value has a fixed bit width irrespective of the bit width of the destination operand being written thereto. Instead of adding these zero values everywhere in the data path, they are instead represented by zero flags in at least the physical registers utilised for register renaming operations and in the result queue prior to results being written to the architectural register file. This saves circuitry resources and reduces energy consumption.

Abstract: A processor core supports execution of program instruction from both a first instruction set and a second instruction set. An architectural register file 18 containing architectural registers is shared by the two instruction sets. The two instruction sets employ logical register specifiers which for at least some values of those logical registers specifiers correspond to different architectural registers within the architectural register file 18. A first decoder 4 for the first instruction set and a second decoder 6 for the second instruction set serve to decode the logical register specifiers to a common register addressing format. This common register addressing format is used to supply register specifiers to renaming circuitry 10 for supporting register renaming in conjunction with a physical register file 16 and an architectural register file 18.

Abstract: An out-of-order renaming processor is provided with a register file within which aliasing between registers of different sizes may occur. In this way a program instruction having a source register of a double precision size may alias with two single precision registers being used as destinations of one or more preceding program instructions. In order to track this data dependency the double precision register may be remapped into a micro-operation specifying two single precision registers as its source register. In this way, scheduling circuitry may use its existing hazard detection and management mechanisms to handle potential data hazards and dependencies. Not all program instructions having such data hazards between registers of different sizes are handled by this source register remapping. For these other program instructions a slower mechanism for dealing with the data dependency hazard is provided.

Abstract: The present invention provides a compound of a formula (I): wherein the variables are defined herein; to a process for preparing such a compound; and to the use of such a compound in the treatment of a PDE4 mediated disease state.

Abstract: A processor 2 includes instruction decoding circuitry 8 and processing circuitry 16, 18, 20, 22, 24. The instruction decoding circuitry decodes at least one conditional program instruction in accordance with a conditional prediction as one of, in accordance with the condition prediction being a condition pass, one or more micro-operation instructions that control the processing circuitry to perform the processing action together with a condition resolution micro-operation instruction, or in accordance with the condition prediction being a condition fail, at least a condition resolution micro-operation instruction. Condition resolution circuitry 24 responds to the condition resolution micro-operation instruction to determine if the condition prediction is incorrect.

Abstract: An out-of-order processor 4 groups program instructions together to control their commitment to complete processing. If an instruction within a group has a source operand dependent upon a plurality of destination operands of other instructions then this is identified as a size mismatch hazard. When the program instruction having the size mismatch hazard reaches a commit point within the processor, then it is flushed together with any speculatively executed succeeding program instructions. Furthermore, the group of program instructions containing the program instruction containing the program instruction having the size mismatch is divided into a plurality of groups of program instructions each containing a single program instruction which are then replayed through the processing mechanisms.