Abstract: Defibrillators, software and methods are provided, for transmitting inaudible audio information to one or more external personal sound devices. The audio information may encode an audible indication, which can thus be played by an external personal sound device to a user such as a rescuer.

Abstract: Defibrillators, software and methods are provided, for issued verbal prompts to rescuers. A defibrillator may receive a muting input and, responsive thereto, cause a verbal prompt to not be issued or to be issued less loudly relative another verbal prompt.

Abstract: Defibrillators, software and methods are provided, for transmitting inaudible audio information to one or more external personal sound devices. The audio information may encode an audible indication, which can thus be played by an external personal sound device to a user such as a rescuer.

Abstract: Defibrillators, software and methods are provided, for issued verbal prompts to rescuers. A defibrillator may receive a muting input and, responsive thereto, cause a verbal prompt to not be issued or to be issued less loudly relative another verbal prompt.

Abstract: In general, the invention facilitates improved inter-module communication within a medical device system, such as an automated external defibrillator (AED), by using a serial data interface based on the USB specification to transfer data between modules. As a result, data transmission rates may be improved significantly, thereby providing ample communication bandwidth for a variety of medical device applications. Further, the serial interconnect nature of the USB interface reduces the number of physical interconnects that are needed to support the interface, thereby reducing the design constraints on the medical device system.

Abstract: A configurable decode circuit for decoding in a block architected SRAM. The configurable decode circuit comprising a decode circuit (10) which decodes through a process of deselection, a first buffer circuit (12) for buffering decode circuit (10), a delayed clock signal (15) for enabling first buffer circuit (12), a gated transmission means (13) for decoupling first buffer circuit from second buffer circuit (14), second buffer circuit (14) for driving capacitive loads, and a means for delaying driver output (16) for enabling gated transmission means (13). The decode circuit (10) is built for simplifying synthesis of the layout of a configurable decode circuit for varying configurations. The configurable decode optimizes performance by reducing the number of circuits in the critical delay path and minimizing capacitive loading on internal circuit nodes.