Abstract: A field effect semiconductor device comprising a high permittivity silicate gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel region 24 formed therein. A metal silicate gate dielectric layer 36 is formed over this substrate, followed by a conductive gate 38. Silicate layer 36 may be, e.g., hafnium silicate, such that the dielectric constant of the gate dielectric is significantly higher than the dielectric constant of silicon dioxide. However, the silicate gate dielectric may also be designed to have the advantages of silicon dioxide, e.g. high breakdown, low interface state density, and high stability. The present invention includes methods for depositing both amorphous and polycrystalline silicate layers, as well as graded composition silicate layers.

Abstract: This invention pertains generally to forming thin oxides at low temperatures, and more particularly to forming uniformly thick, thin oxides. We disclose a low temperature method for forming a thin, uniform oxide 16 on a silicon surface 12. This method includes providing a partially completed integrated circuit on a semiconductor substrate 10 with a clean, hydrogen terminated or atomically flat, silicon surface 12; and stabilizing the substrate at a first temperature. The method further includes exposing the silicon surface to an atmosphere 14 including ozone, while maintaining the substrate 10 at the first temperature. In this method, the exposing step creates a uniformly thick, oxide film 16. This method is suitable for room temperature processing.

Abstract: An embodiment of the instant invention is a method of forming a electrically conductive structure insulatively disposed from a second structure, the method comprising: providing the second structure; forming the electrically conductive structure of a material (step 118 of FIG. 1) that remains substantially conductive after it is oxidized; forming an electrically insulative layer (step 116 of FIG. 1) between the second structure and the conductive structure; and oxidizing the conductive structure by subjecting it to an ozone containing atmosphere for a duration of time and at a first temperature.

Abstract: A field effect semiconductor device comprising a high permittivity silicate gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel region 24 formed therein. A metal silicate gate dielectric layer 36 is formed over this substrate, followed by a conductive gate 38. Silicate layer 36 may be, e.g., hafnium silicate, such that the dielectric constant of the gate dielectric is significantly higher than the dielectric constant of silicon dioxide. However, the silicate gate dielectric may also be designed to have the advantages of silicon dioxide, e.g. high breakdown, low interface state density, and high stability. The present invention includes methods for depositing both amorphous and polycrystalline silicate layers, as well as graded composition silicate layers.

Abstract: A method of fabricating an electronic device over a semiconductor substrate, the method comprising the steps of: forming a conductive structure over the semiconductor substrate (step 106 of FIG. 1); and forming a layer of high-dielectric constant material between the conductive structure and the semiconductor substrate (step 102 of FIG. 1), the layer of high-dielectric constant material is formed by supplying a gaseous silicon source and a second gaseous material which is comprised of a material selected from the group consisting of: Hf, Zr, La, Y, Sc, Ce and any combination thereof.

Abstract: A method of forming an annealed high-K metal oxide transistor gate structure is disclosed. A metal oxide layer is formed over a semiconductor substrate. The metal oxide layer undergoes a buffered annealed process in an oxygen atmosphere to anneal the metal oxide layer at or below the thermodynamic chemical equilibrium of SiO/SiO2 and at or above the thermodynamic chemical equilibrium of the metal oxide layer.

Abstract: An embodiment of the instant invention is a method of forming a semiconductor device situated over a semiconductor substrate, the method comprising the steps of: forming a layer of suboxide material (layer 206 of FIG. 2a) over the substrate (substrate 202 of FIGS. 2a-2c), the suboxide material comprised of a material selected from the group consisting of: HfSiOx, ZrSiOx, LaSiOx, YSiOx, ScSiOx, and CeSiOx; and forming a structure (layer 210 of FIG. 2c) on the layer of suboxide material. In an alternative embodiment, semiconductor device is a transistor where and the structure formed on the layer of suboxide material is a gate electrode (preferably comprised of: polycrystalline silicon, tungsten, titanium, tungsten nitride, titanium nitride, platinum, aluminum, and any combination thereof.

Abstract: A method for forming a thermal silicon nitride on a semiconductor substrate is disclosed. This method allows formation of thermal silicon nitride that is thick enough for a FET gate dielectric, but has a low thermal budget.

Abstract: A method of forming an annealed high-K metal oxide transistor gate structure is disclosed. A metal oxide layer is formed over a semiconductor substrate. The metal oxide layer undergoes a buffered annealed process in an oxygen atmosphere to anneal the metal oxide layer at or below the thermodynamic chemical equilibrium of SiO/SiO2 and at or above the thermodynamic chemical equilibrium of the metal oxide layer.

Abstract: A method of fabricating an electronic device over a semiconductor substrate, the method comprising the steps of: forming a conductive structure over the semiconductor substrate (step 106 of FIG. 1); and forming a layer of high-dielectric constant material between the conductive structure and the semiconductor substrate (step 102 of FIG. 1), the layer of high-dielectric constant material is formed by supplying a gaseous silicon source and a second gaseous material which is comprised of a material selected from the group consisting of: Hf, Zr, La, Y, Sc, Ce and any combination thereof.

Abstract: A method for forming a thermal silicon nitride on a semiconductor substrate is disclosed. This method allows formation of thermal silicon nitride that is thick enough for a FET gate dielectric, but has a low thermal budget.

Abstract: A method for forming a thermal silicon nitride on a semiconductor substrate is disclosed. This method allows formation of thermal silicon nitride that is thick enough for a FET gate dielectric, but has a low thermal budget.

Abstract: A field effect semiconductor device comprising a high permittivity hafnium (or hafnium-zirconium) nitride gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel region 24 formed therein. A hafnium (or hafnium-zirconium) nitride gate dielectric layer 36 is formed over this substrate, followed by a conductive gate 38. Hafnium (or hafnium-zirconium) nitride gate dielectric layer 36 has a dielectric constant is significantly higher than the dielectric constant of silicon dioxide.

Abstract: A method of fabricating an electronic device over a semiconductor substrate, the method comprising the steps of: forming a conductive structure over the semiconductor substrate (step 106 of FIG. 1); and forming a layer of high-dielectric constant material between the conductive structure and the semiconductor substrate (step 102 of FIG. 1), the layer of high-dielectric constant material is formed by supplying a gaseous silicon source and a second gaseous material which is comprised of a material selected from the group consisting of: Hf, Zr, La, Y, Sc, Ce and any combination thereof.

Abstract: A method of fabricating a transistor using silicon on lattice matched insulator. A first monocrystalline silicon layer is provided and a first layer of dielectric is epitaxially deposited over the first silicon layer substantially lattice matched with the first silicon layer and substantially monocrystalline. A first electrically conductive gate electrode is epitaxially formed over the first layer of dielectric substantially lattice matched with the first layer of dielectric. A second layer of dielectric is epitaxially deposited conformally over the first gate electrode and exposed portions of first layer of dielectric substantially lattice matched with the first silicon layer and substantially monocrystalline. A second monocrystalline silicon layer is epitaxially deposited over the second layer of dielectric and a third layer of dielectric is epitaxially deposited over the second silicon layer substantially lattice matched with the first silicon layer and substantially monocrystalline.

Abstract: An apparatus and method for evaluating semiconductor structures and devices are provided. A method for evaluating at least one selected electrical property of a semiconductor device (201) in relation to a selected geometric dimension of the semiconductor device (201). The method further includes forming a plurality of semiconductor devices (201) on a substrate (202), the devices (201) having at least one geometric dimension, measuring the at least one electrical property of at least one of the semiconductor devices (201) using a scanning probe microscopy based technique, and determining a relationship between the measured electrical property and the selected geometric dimension of the semiconductor device (201). The method further includes evaluating at least one semiconductor fabrication process based upon the determined relationship.

Abstract: A field effect semiconductor device comprising a high permittivity hafnium (or hafnium-zirconium) nitride gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel region 24 formed therein. A hafnium (or hafnium-zirconium) nitride gate dielectric layer 36 is formed over this substrate, followed by a conductive gate 38. Hafnium (or hafnium-zirconium) nitride gate dielectric layer 36 has a dielectric constant is significantly higher than the dielectric constant of silicon dioxide.

Abstract: An integrated circuit capacitor comprising a high permittivity dielectric and a method of forming the same are disclosed herein. In one embodiment, this capacitor may be used as a DRAM storage cell. For example, a DRAM storage node electrode 22 may be formed of polysilicon. An ultrathin oxynitride passivation layer 25 (e.g. less than 1 nm) is formed on this electrode by exposure of the substrate to NO. A tantalum pentoxide layer 24 is formed over layer 25, followed by a cell plate 26. Passivation layer 25 allows electrode 22 to resist oxidation during deposition of layer 25, thus preventing formation of an interfacial oxide layer. A passivation layer formed by this method may typically be deposited with shorter exposure times and lower temperatures than nitride passivation layers.

Abstract: A field effect semiconductor device comprising a high permittivity hafnium (or hafnium-zirconium) nitride gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel region 24 formed therein. A hafnium (or hafnium-zirconium) nitride gate dielectric layer 36 is formed over this substrate, followed by a conductive gate 38. Hafnium (or hafnium-zirconium) nitride gate dielectric layer 36 has a dielectric constant is significantly higher than the dielectric constant of silicon dioxide.

Abstract: A method of making a semiconductor device and the device. The device, according to a first embodiment, is fabricated by providing a silicon (111) surface, forming on the surface a dielectric layer of crystalline silicon nitride and forming an electrode layer on the dielectric layer of silicon nitride. The silicon (111) surface is cleaned and made atomically flat. The dielectric layer if formed of crystalline silicon nitride by placing the surface in an ammonia ambient at a pressure of from about 1×10−7 to about 1×10−5 Torr at a temperature of from about 850° C. to about 1000° C. The electrode layer is heavily doped silicon. According to a second embodiment, there is provided a silicon (111) surface on which is formed a first dielectric layer of crystalline silicon nitride having a thickness of about 2 monolayers.