Abstract: A wafer-on-wafer formed memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. The memory die can be formed as one of many memory dies on a first semiconductor wafer. The logic die can be formed as one of many logic dies on a second semiconductor wafer. The first and second wafers can be bonded via a wafer-on-wafer bonding process. The memory and logic device can be singulated from the bonded first and second wafers.

Abstract: The present disclosure includes apparatuses and methods for data movement. An example apparatus includes a memory device that includes a plurality of subarrays of memory cells and sensing circuitry coupled to the plurality of subarrays. The sensing circuitry includes a sense amplifier and a compute component. The memory device also includes a plurality of subarray controllers. Each subarray controller of the plurality of subarray controllers is coupled to a respective subarray of the plurality of subarrays and is configured to direct performance of an operation with respect to data stored in the respective subarray of the plurality of subarrays. The memory device is configured to move a data value corresponding to a result of an operation with respect to data stored in a first subarray of the plurality of subarrays to a memory cell in a second subarray of the plurality of subarrays.

Abstract: A processing unit (PU) controller is described herein. A memory device that includes a bank controller and the PU controller can also include a plurality of banks of memory cells. The PU controller can be coupled to the plurality of banks of memory cells. The PU controller can also comprise a PU. The bank controller can provide data from the plurality of banks to the PU controller. The PU controller can receive the data from any of the plurality of banks. The PU controller can also provide the data to the PU. The PU can perform a plurality of operations utilizing the data.

Abstract: Methods, systems, and devices related to sense amplifiers of a memory device serving as a Static Random Access Memory (SRAM) cache. For example, a memory array can be coupled to sense amplifiers. In a first mode, the sense amplifiers can be electrically disconnect from digit lines of the memory array. In the first mode, data and metadata of a cache line can be stored in the sense amplifiers when electrically disconnected from the number of digit lines. In the first mode, a portion of the data can be communicated, based on the metadata, from the sense amplifiers to the processing device. In a second mode, the sense amplifiers can connect to the memory array and sense data from the memory array.

Abstract: Systems, apparatuses, and methods related to storage device operation orchestration are described. A plurality of computing devices (or “tiles”) can be coupled to a controller (e.g., an “orchestration controller”) and an interface. The controller can control operation of the computing devices. For instance, the controller can include circuitry to request a block of data from a memory device coupled to the apparatus, cause a processing unit of at least one computing device of the plurality of computing devices to perform an operation on the block of data in which at least some of the data is ordered, reordered, removed, or discarded, and cause, after some of the data is ordered, reordered, removed, or discarded, the block of data to be transferred to the interface coupled to the plurality of computing devices.

Abstract: Methods, systems, and devices related to sense amplifiers of a memory device serving as a Static Random Access Memory (SRAM) resource. For example, a memory array of a memory device can be coupled to sense amplifiers. The sense amplifiers can be electrically disconnected from digit lines of the memory array. Data can be stored in the sense amplifiers. The data can be communicated from the sense amplifiers to a processing device external to the memory array and the sense amplifiers. The sense amplifiers can receive data from the processing device and, when electrically disconnected from the number of digit lines, store the received data.

Abstract: A processing unit of memory for table lookup is described herein. A plurality of elements (e.g., output values) of a lookup table (LUT) can be sequentially prefetched from a respective column of memory cells that is indicated by each vector value of vector values stored in positions of a register of the processing unit. Each of the vector values can be shifted by one position among the positions of the register to cause a terminal position of the register to be available for storing the respective output value among the prefetched output values.

Abstract: A wafer-on-wafer bonded memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. A memory device formed on a memory die can include many global input/output lines and many arrays of memory cells. Each array of memory cells can include respective local input/output (LIO) lines coupled to a global input/output line. A logic device can be formed on a logic die. A bond, formed between the memory die and the logic die via a wafer-on-wafer bonding process, can couple the many global input/output lines to the logic device.

Abstract: The processing unit (PU) PU of a memory device can receive a matrix of data values and a vector of data values stored in a bank. The PU can perform a first plurality of multiplication operations on a first data value of the vector utilizing a first plurality of data values of a first column of the matrix. The first plurality of multiplication operations can be performed by a plurality of multiply-accumulate (MAC) units. Each of the first plurality of multiplication operations can be performed by a different MAC unit of the plurality of MAC units. The PU can perform a second plurality of multiplication operations on a second data value of the vector utilizing a second plurality of data values of a second column of the matrix. Each of the second plurality of multiplication operations can be performed by a different MAC unit of the plurality of MAC units.

Abstract: A crossbar and/or multiplexors (MUXs) of a memory device can be utilized to provide row and column access of a matrix stored in an array of the memory device. The crossbar can couple input lines to the crossbar to output lines from the crossbar in a particular configuration, where the output lines couple the crossbar to the array. The crossbar can receive data values of a matrix via the input lines. The crossbar can also provide the data values to the array via the output lines. The particular configuration allows the data values provided to the array to be sensed as columns of the data values of the matrix and rows of the data values of the matrix.

Abstract: Double bank prefetch is described herein. A first sense amplifier strip couped to the array of memory cells and the column decoder can receive first data from the array of memory cells and provide the first data to a first processing unit (PU) of the apparatus using the address. The second sense amplifier strip coupled to the array and the column decoder can receive second data from the array of memory cells and provide the second data to a second PU of the apparatus using the address.

Abstract: A multiplexor (MUX) for a processing unit of memory is described herein. The MUX and a plurality of multiply-accumulate (MAC) units coupled to the MUX can receive a plurality of data values. The MUX can provide a first half of the plurality of data values to the plurality of MAC units during a first half of a duration of time and can provide a second half of the plurality of data values to the plurality of MAC units during a second half of the duration of time. The plurality of MAC units can perform a first plurality of multiplication operations utilizing the first half of the plurality of data values and can perform a second plurality of multiplication operations utilizing the second half of the plurality of data values.

Abstract: A memory device can include a first error correction code (ECC) circuitry, a second ECC circuitry, and a multiplexor (MUX). The first ECC circuitry receive first data from a first bank. The second ECC circuitry can receive second data from a second bank. A MUX can receive the first data from the first ECC circuitry and the second data from the second ECC circuitry. The MUX can provide the first data in a first portion of a duration of time. The MUX can provide the second data in a second portion of the duration of time. A processing unit (PU) can perform a first plurality of multiplication operations utilizing the first data provided by the MUX during the first portion of the duration of time and a second plurality of multiplication operations utilizing the second data provided by the MUX during the second portion of the duration of time.

Abstract: Coupling processing units to data buses in memory is described herein. A data bus coupled to an array of memory cells can receive first data. A processing unit (PU) can be coupled to the data bus. The PU can receive the first data from the data bus. The PU can perform a plurality of operations utilizing the first data to generate second data. The PU can provide the second data to the data bus to store the second data in the array of memory cells.

Abstract: The present disclosure includes apparatuses and methods for data movement. An example apparatus includes a memory device that includes a plurality of subarrays of memory cells and sensing circuitry coupled to the plurality of subarrays. The sensing circuitry includes a sense amplifier and a compute component. The memory device also includes a plurality of subarray controllers. Each subarray controller of the plurality of subarray controllers is coupled to a respective subarray of the plurality of subarrays and is configured to direct performance of an operation with respect to data stored in the respective subarray of the plurality of subarrays. The memory device is configured to move a data value corresponding to a result of an operation with respect to data stored in a first subarray of the plurality of subarrays to a memory cell in a second subarray of the plurality of subarrays.

Abstract: A memory device includes a memory die bonded to a logic die. A logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and memory die. The logic die can also receive signals indicative of kernel data from local input/output (LIO) lines of the memory die and through the bond. The logic die can perform a plurality of operations at a plurality of vector-vector (VV) units utilizing the signals indicative of input data and the signals indicative of kernel data.

Abstract: An apparatus comprising an array of memory cells, a register coupled to the array of memory cells, and control logic coupled to the register and the array of memory cells. The control logic is configured to issue an internal command in response to a memory controller receiving an external command, generate an address corresponding to the internal command, provide the internal command to a row decoder and a column decoder, and instruct a processing unit (PU) to perform multiply-accumulate (MAC) operations on received data.

Abstract: Address offset in memory is described herein. The controller of a memory device can receive an address associated with a bank of memory cells. The controller can access an address offset value that corresponds to the bank of memory cells. The controller can update the address utilizing the address offset value. The controller can provide the updated address to a row decoder. The row decoder can receive the updated address and activate a row of a bank of memory cells utilizing the updated address.

Abstract: The present disclosure includes apparatuses and methods for parallel writing to multiple memory device locations. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller in the memory device is configured to receive a block of resolved instructions and/or constant data from the host. The memory controller is configured to write the resolved instructions and/or constant data in parallel to a plurality of locations the memory device.

Abstract: Apparatuses and methods related to mitigating unauthorized memory access are described. Mitigating unauthorized memory access can include verifying whether an access command is authorized to access a protected region of a memory array. The authorization can be verified utilizing a key and a memory address corresponding to the access command. If an access command is authorized to access a protected region, then a row of the memory array corresponding to the access command can be activated. If an access command is not authorized to access the protected region, then a row of the memory array corresponding to the access command may not be activated.