Patents by Inventor Glen E. Leinbach

Glen E. Leinbach has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7518384
    Abstract: One or more test probe access structures for accessing vias on a printed circuit assembly and method of fabrication thereof is presented. Each test probe access structure is conductively connected to a via at a test probe access location above an exposed surface of a via to be accessible for probing by a test probe.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: April 14, 2009
    Assignee: Agilent Technologies, Inc.
    Inventors: Glen E Leinbach, Kenneth P Parker
  • Publication number: 20080083816
    Abstract: Methods and systems for improving a solder paste stenciling process include obtaining data pertaining to solder paste deposits on a printed circuit board, the solder paste deposits deposited by a solder paste stenciling process through multiple identical apertures of a solder paste stencil, statistically analyzing the data, and correlating the data with a plurality of solder paste stenciling process problems to identify at least one solder paste stenciling process problem in the solder paste stenciling process.
    Type: Application
    Filed: October 4, 2006
    Publication date: April 10, 2008
    Inventors: Glen E. Leinbach, Stacy Kalisz Johnson
  • Patent number: 7307222
    Abstract: A test access point structure for accessing test points of a printed circuit board and method of fabrication thereof is presented. In an x-, y-, z-coordinate system where traces are printed along an x-y plane, the z-dimension is used to implement test access point structures. Each test access point structure is conductively connected to a trace at a test access point directly on top of the trace and along the z axis of the x-, y-, z-coordinate system above an exposed surface of the printed circuit board to be accessible for electrical probing by an external device.
    Type: Grant
    Filed: September 24, 2003
    Date of Patent: December 11, 2007
    Assignee: Agilent Technologies, Inc.
    Inventors: Kenneth P. Parker, Ronald J. Peiffer, Glen E. Leinbach
  • Patent number: 6911738
    Abstract: An assembly and method for detecting defective and open solder joints of an area array packages attached to a printed circuit assembly is presented. The assembly employs offset pad layout on either or both of the printed circuit assembly or the area array package allowing improved solder joint defect detection.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: June 28, 2005
    Assignee: Agilent Technologies, Inc.
    Inventor: Glen E. Leinbach