Abstract: A flip-flop having one or more stages (e.g., a master stage and a slave stage in a master-slave flip-flop, or a single stage as in a latch), at least one stage having a driver coupled at its input and output to a feedback path with a gated inverter having embedded preset and/or clear logic. By embedding the preset/clear logic in the feedback path, the driver can be implemented using a simple inverter. Moreover, the preset and/or clear functionality can be added without adversely affecting either the setup time or the clock-to-Q propagation time of the flip-flop.

Abstract: A fast, low power and small size approach to matching digital patterns provides for comparing of the input pattern bit-by-bit against the reference pattern to determine matches. In the illustrative embodiment, each mismatch turns on a current source. When the current from mismatches exceeds a maximum current sink value, the pattern mismatch output goes high. Both the reference pattern as well as the number of bits that must match may conveniently be made programmable. This approach is especially useful in "fuzzy" matching, where any N bits of an M bit pattern must match to consider the pattern matched.

Abstract: An asynchronous to synchronous interface between a master chip and a target chip, the interface being located on the target chip, includes a synchronous write logic unit and one set of synchronous transfer latches. A system clock (clock on target chip) and asynchronous clock signal are connected to the synchronous write logic unit. The asynchronous clock signal is also connected to a set of asynchronous latches, which receive data from the master chip upon receiving active asynchronous clock signals. The asynchronous latches are connected to a set of synchronous latches. The synchronous latches are controlled by a synchronous write signal generated by the synchronous write logic unit. Based on the asynchronous write signal and clock signal of the target chip the synchronous write logic unit synchronously transfers data from the outputs of the asynchronous latches to the outputs of the synchronous latches.

Abstract: A novel mad/write control register uses the same bus port for reading and writing, while requiting only one unique control line. The technique may be implemented as a "D" type level sense latch. The write operation is similar to standard latch operation: the transmission gate on the D input is turned on while the feedback transmission gate is off. However, for read operation, both transmission gates are enabled, thereby allowing the register output value to drive the bus. A preset or clear capability may optionally be provided. This approach reduces the size of the register as compared to standard read/write registers, and requires only one unique control line versus two, thus reducing decoding logic and routing. Since only one port to the bus is required, the bus load gate capacitance is typically one-half that of the standard approach.

Abstract: An integrated circuit input buffer is adapted to operate at either of two input levels, typically either TTL or CMOS logic levels. This is accommplished by switching an additional transistor (e.g. 15) into a path between the output node (e.g. 12) and a power supply voltage (e.g. V.sub.DD), thereby changing the ratio of the pull-up to pull-down devices. The desired input level may be selected after the manufacture of the device, as by applying a voltage to a package terminal, or by programming a register during operation of the integrated circuit.