Abstract: Embodiments of the present disclosure relate to separating an integrated circuit (IC) structure from an adjacent chip. An IC structure according to embodiments of the disclosure may include: a semiconductor region including an interconnect pad positioned thereon, the interconnect pad electrically connected to a solder bump; and an ohmic heating wire positioned within the semiconductor region and in thermal communication with the interconnect pad, wherein the ohmic heating wire is configured to be heated above a melting temperature of the solder bump.

Abstract: Methods and apparatus for joining a chip with a substrate. The chip is moved by with a pick-and-place machine from a first location to a second location proximate to the substrate over a first time. In response to moving the chip in a motion path from the first location to the second location, a plurality of solder bumps carried on the chip are liquefied over a second time that is less than the first time. While the solder bumps are liquefied, the chip is placed by the pick-and-place machine onto the substrate.

Abstract: Disclosed are processes and apparatuses for semiconductor die removal and rework, including thin dies. In one aspect the process involves the use of a localized induction heating system to melt targeted solder joints, thereby minimizing the degradation of the thermal performance of the assembly undergoing the rework. Use of a vacuum-based die removal head, optionally in combination with the induction heating system, allows for the removal of thin dies of 150 micrometers thick or less.

Abstract: Embodiments of the present disclosure relate to separating an integrated circuit (IC) structure from an adjacent chip. An IC structure according to embodiments of the disclosure may include: a semiconductor region including an interconnect pad positioned thereon, the interconnect pad electrically connected to a solder bump; and an ohmic heating wire positioned within the semiconductor region and in thermal communication with the interconnect pad, wherein the ohmic heating wire is configured to be heated above a melting temperature of the solder bump.

Abstract: Methods and apparatus for joining a chip with a substrate. The chip is moved by with a pick-and-place machine from a first location to a second location proximate to the substrate over a first time. In response to moving the chip in a motion path from the first location to the second location, a plurality of solder bumps carried on the chip are liquefied over a second time that is less than the first time. While the solder bumps are liquefied, the chip is placed by the pick-and-place machine onto the substrate.

Abstract: Methods and apparatus for joining a chip with a substrate. The chip is moved by with a pick-and-place machine from a first location to a second location proximate to the substrate over a first time. In response to moving the chip in a motion path from the first location to the second location, a plurality of solder bumps carried on the chip are liquefied over a second time that is less than the first time. While the solder bumps are liquefied, the chip is placed by the pick-and-place machine onto the substrate.

Abstract: Methods and structures provide an electrostatic discharge (ESD) indicator including an electric field sensitive material configured to undergo a specific color change in response to an electric field. An exposure of the structure to an ESD can be visually determined via the specific color change of the ESD indicator.

Abstract: A semiconductor structure in the form of a die comprises a silicon-containing core having a first surface, an opposite second surface and a peripheral edge surface. A circuit structure on the first surface is circumscribed by a peripheral crackstop structure which stops short of the second surface, thereby leaving an accessible portion of the peripheral edge surface free of the crackstop structure. One or more angular or orthogonal edge connector through-silicon conductive vias (“edge connector TSVs”) connect the circuit structure to the accessible portion of the peripheral edge surface without penetrating the crackstop structure. A method of making the structure includes forming the edge connector TSVs in the silicon wafer from which the semiconductor structures, i.e., dies, are cut.

Abstract: A semiconductor structure in the form of a die comprises a silicon-containing core having a first surface, an opposite second surface and a peripheral edge surface. A circuit structure on the first surface is circumscribed by a peripheral crackstop structure which stops short of the second surface, thereby leaving an accessible portion of the peripheral edge surface free of the crackstop structure. One or more angular or orthogonal edge connector through-silicon conductive vias (“edge connector TSVs”) connect the circuit structure to the accessible portion of the peripheral edge surface without penetrating the crackstop structure. A method of making the structure includes forming the edge connector TSVs in the silicon wafer from which the semiconductor structures, i.e., dies, are cut.

Abstract: Disclosed are processes and apparatuses for semiconductor die removal and rework, including thin dies. In one aspect the process involves the use of a localized induction heating system to melt targeted solder joints, thereby minimizing the degradation of the thermal performance of the assembly undergoing the rework. Use of a vacuum-based die removal head, optionally in combination with the induction heating system, allows for the removal of thin dies of 150 micrometers thick or less.

Abstract: In an approach to determining reliability test strategy, one or more computer processors receive a volume forecast for manufacturing one or more products. The one or more computer processors receive information describing the one or more products. The one or more computer processors retrieve reliability test requirements associated with the one or more products. The one or more computer processors retrieve reliability test capability of one or more reliability test vendors. The one or more computer processors determine, based, at least in part, on the volume forecast, the information describing the one or more products, the reliability test requirements, and the reliability test capability of the one or more reliability test vendors, a reliability test strategy.

Abstract: Underfill materials and methods for removing an underfill material from beneath a chip in relation to removal of the chip from a substrate. The underfill material may a plurality of particles dispersed in a bulk matrix. The material constituting the particles may be capable of generating heat energy when exposed to a time-varying magnetic field. The bulk matrix of the underfill material between the chip and a substrate may be heated with heat energy transferred from the particles. While heated, the underfill material is removed. The heating of the underfill material may also be used to heat solder bumps connecting the chip with the substrate so that the solder bumps are liquefied.

Abstract: Underfill materials and methods for removing an underfill material from beneath a chip in relation to removal of the chip from a substrate. The underfill material may a plurality of particles dispersed in a bulk matrix. The material constituting the particles may be capable of generating heat energy when exposed to a time-varying magnetic field. The bulk matrix of the underfill material between the chip and a substrate may be heated with heat energy transferred from the particles. While heated, the underfill material is removed. The heating of the underfill material may also be used to heat solder bumps connecting the chip with the substrate so that the solder bumps are liquefied.

Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure with a recessed solder bump area, and methods of forming the same. An IC structure according to embodiments of the present disclosure can include: a semiconductor material, wherein an upper surface of the semiconductor material includes a non-recessed area and a recessed area laterally separated from each other, the recessed area of the upper surface being shaped to receive a solder bump therein; at least one first through-semiconductor via (TSV) positioned within the semiconductor material and including an upper surface protruding from the recessed area of the semiconductor material; and a metal layer formed over the recessed area and electrically connected to the at least one first TSV.

Abstract: In an approach to determining reliability test strategy, one or more computer processors receive a volume forecast for manufacturing one or more products. The one or more computer processors receive information describing the one or more products. The one or more computer processors retrieve reliability test requirements associated with the one or more products. The one or more computer processors retrieve reliability test capability of one or more reliability test vendors. The one or more computer processors determine, based, at least in part, on the volume forecast, the information describing the one or more products, the reliability test requirements, and the reliability test capability of the one or more reliability test vendors, a reliability test strategy.

Abstract: Methods and structures provide an electrostatic discharge (ESD) indicator including an electric field sensitive material configured to undergo a specific color change in response to an electric field. An exposure of the structure to an ESD can be visually determined via the specific color change of the ESD indicator.

Abstract: A method of applying inductive heating to join an integrated circuit chip to an electrical substrate using solder bumps including applying a magnetic field to a magnetic liner in thermal contact with a solder bump on the integrated circuit chip. The magnetic field causes Joule heating in the magnetic liner sufficient to melt the solder bump, which has a lower portion embedded in a first dielectric layer and an upper portion at least partially embedded in a second dielectric layer. The lower portion is in electrical contact with a conductive pad, the first dielectric layer is above the conductive pad and the second dielectric layer is on top of the first dielectric layer. The duration of application of the magnetic field is controlled to achieve a joining temperature that is approximately halfway between the storage and operating temperatures of the integrated circuit chip.

Abstract: Embodiments of the present invention provide a semiconductor structure and method to reduce thermal energy transfer during chip-join processing. In certain embodiments, the semiconductor structure comprises a thermal insulating element formed under a first conductor. The semiconductor structure also comprises a solder bump formed over the first conductor. The semiconductor structure further comprises a second conductor formed on a side of the thermal insulating element and in electrical communication with the first conductor and a third conductor. The third conductor is formed to be in thermal or electrical communication with the thermal insulating element. The thermal insulating element includes thermal insulating material and the thermal insulating element is structured to reduce thermal energy transfer during a chip-join process from the solder bump to a metal level included in the semiconductor structure.

Abstract: A method of applying inductive heating to join an integrated circuit chip to an electrical substrate using solder bumps including applying a magnetic field to a magnetic liner in thermal contact with a solder bump on the integrated circuit chip, the magnetic field causes Joule heating in the magnetic liner sufficient to melt the solder bump, the solder bump comprising a lower portion embedded in a first dielectric layer and an upper portion at least partially embedded in a second dielectric layer, the lower

Abstract: Embodiments of the present invention provide a semiconductor structure and method to reduce thermal energy transfer during chip-join processing. In certain embodiments, the semiconductor structure comprises a thermal insulating element formed under a first conductor. The semiconductor structure also comprises a solder bump formed over the first conductor. The semiconductor structure further comprises a second conductor formed on a side of the thermal insulating element and in electrical communication with the first conductor and a third conductor. The third conductor is formed to be in thermal or electrical communication with the thermal insulating element. The thermal insulating element includes thermal insulating material and the thermal insulating element is structured to reduce thermal energy transfer during a chip-join process from the solder bump to a metal level included in the semiconductor structure.