Patents by Inventor Glen Earl Hush

Glen Earl Hush has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240070801
    Abstract: Systems, methods, and apparatus related to memory devices. In one approach, an artificial intelligence system uses a memory device to provide inference results. Image data from a camera is provided to the memory device. The memory device stores the image data received from the camera. The memory device includes dynamic random access memory (DRAM), and static random access memory (SRAM). The memory device also includes a processor to run a neural network. The neural network uses the image data as input. An output from the neural network provides an inference result. In one example, the memory device has a same form factor as a conventional DRAM device. The memory device includes a multiply-accumulate (MAC) engine that supports computations for the neural network.
    Type: Application
    Filed: August 31, 2022
    Publication date: February 29, 2024
    Inventors: Xinyu Wu, Timothy Paul Finkbeiner, Peter Lawrence Brown, Troy Dale Larsen, Glen Earl Hush, Troy Allen Manning
  • Patent number: 8924803
    Abstract: The invention provides a boundary scan test interface circuit. The boundary scan test interface circuit includes N test input pads, a test interfacing module and M test output pads, wherein N and M are positive integers, and M is smaller than N. The test interfacing module is coupled to the test input pads. The test interfacing module having a plurality of logical gates, and each of input pins of each of the logical gates coupled to each of the test input pads. The test output pads are coupled to output pins of the logical gates in the test interfacing module.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: December 30, 2014
    Assignee: Nanya Technology Corporation
    Inventors: Glen Earl Hush, Jeffrey P Wright
  • Publication number: 20140108877
    Abstract: The invention provides a boundary scan test interface circuit. The boundary scan test interface circuit includes N test input pads, a test interfacing module and M test output pads, wherein N and M are positive integers, and M is smaller than N. The test interfacing module is coupled to the test input pads. The test interfacing module having a plurality of logical gates, and each of input pins of each of the logical gates coupled to each of the test input pads. The test output pads are coupled to output pins of the logical gates in the test interfacing module.
    Type: Application
    Filed: October 17, 2012
    Publication date: April 17, 2014
    Inventors: Glen Earl Hush, Jeffrey P. Wright