Abstract: Ferroelectric memory cells (3) are presented, in which a cell resistor (R) is integrated into the cell capacitor (C) to inhibit charge accumulation or charge loss at the cell storage node (SN) when the cell (3) is not being accessed while avoiding significant disruption of memory cell access operations. Methods (100, 200) are provided for fabricating ferroelectric memory cells (3) and ferroelectric capacitors (C), in which a parallel resistance (R) is integrated in the capacitor ferroelectric material (20) or in an encapsulation layer (46) formed over the patterned capacitor structure (C).

Abstract: Ferroelectric memory cells (3) are presented, in which a cell resistor (R) is integrated into the cell capacitor (C) to inhibit charge accumulation or charge loss at the cell storage node (SN) when the cell (3) is not being accessed while avoiding significant disruption of memory cell access operations. Methods (100, 200) are provided for fabricating ferroelectric memory cells (3) and ferroelectric capacitors (C), in which a parallel resistance (R) is integrated in the capacitor ferroelectric material (20) or in an encapsulation layer (46) formed over the patterned capacitor structure (C).

Abstract: Ferroelectric capacitors (CFE) are provided, having upper and lower conductive electrodes (22, 18) spaced along an axis (48), and a ferroelectric material (20) between the electrodes, where the ferroelectric material (20) comprises unit cells (200) individually comprising an elongated dimension (c), and where 50-90% of the unit cells in the ferroelectric material are oriented with elongated dimensions substantially parallel to the axis. Methods (100) are provided for fabricating ferroelectric capacitors in a wafer, comprising forming (112) a ferroelectric material above a lower electrode material, the ferroelectric material comprising unit cells with an elongated dimension, wherein 50-90% of the unit cells are oriented with elongated dimensions substantially normal to an upper surface of the wafer.

Abstract: A method for fabrication of ferroelectric capacitor elements of an integrated circuit includes steps of deposition of an electrically conductive bottom electrode layer, preferably made of a noble metal. The bottom electrode is covered with a layer of ferroelectric dielectric material. The ferroelectric dielectric is annealed with a first anneal prior to depositing a second electrode layer comprising a noble metal oxide. Deposition of the electrically conductive top electrode layer is followed by annealing the layer of ferroelectric dielectric material and the top electrode layer with a second anneal. The first and the second anneal are performed by rapid thermal annealing.

Abstract: A bottom electrode structure and manufacturing method is described for producing crystallographically textured iridium electrodes for making textured PZT capacitors that enables enhanced ferroelectric memory performance. The use of seed layers originating from hexagonal crystal structures with {0001} texture provides a smooth surface for growth of {111} textured iridium, which exhibits the face-centered cubic (“FCC”) structure. This seeding technique results in {111} textured iridium with a small surface roughness relative to the film thickness. The highly textured iridium supports {111} textured PZT dielectric layer growth. Textured PZT exhibits enhanced switched polarization, reduced operating voltage and also improves the reliability of PZT capacitors used in FRAM® memory and other microelectronic devices.

Abstract: A bottom electrode structure and manufacturing method is described for producing crystallographically textured iridium electrodes for making textured PZT capacitors that enables enhanced ferroelectric memory performance. The use of seed layers originating from hexagonal crystal structures with {0001} texture provides a smooth surface for growth of {111} textured iridium, which exhibits the face-centered cubic (“FCC”) structure. This seeding technique results in {111} textured iridium with a small surface roughness relative to the film thickness. The highly textured iridium supports {111} textured PZT dielectric layer growth. Textured PZT exhibits enhanced switched polarization, reduced operating voltage and also improves the reliability of PZT capacitors used in FRAM® memory and other microelectronic devices.

Abstract: A charge storage capacitor includes a bottom electrode, a dielectric layer formed on the bottom electrode, and a local interconnect electrode formed on the dielectric layer, wherein the dielectric layer is an encapsulation layer, and a ferroelectric memory cell includes the charge storage capacitor.

Abstract: A bottom electrode structure and manufacturing method is described for producing crystallographically textured iridium electrodes for making textured PZT capacitors that enables enhanced ferroelectric memory performance. The use of seed layers originating from hexagonal crystal structures with {0001} texture provides a smooth surface for growth of {111} textured iridium, which exhibits the face-centered cubic (“FCC”) structure. This seeding technique results in {111} textured iridium with a small surface roughness relative to the film thickness. The highly textured iridium supports {111} textured PZT dielectric layer growth. Textured PZT exhibits enhanced switched polarization, reduced operating voltage and also improves the reliability of PZT capacitors used in FRAM® memory and other microelectronic devices.

Abstract: A bottom electrode structure and manufacturing method is described for producing crystallographically textured iridium electrodes for making textured PZT capacitors that enables enhanced ferroelectric memory performance. The use of seed layers originating from hexagonal crystal structures with {0001} texture provides a smooth surface for growth of {111} textured iridium, which exhibits the face-centered cubic (“FCC”) structure. This seeding technique results in {111} textured iridium with a small surface roughness relative to the film thickness. The highly textured iridium supports {111} textured PZT dielectric layer growth. Textured PZT exhibits enhanced switched polarization, reduced operating voltage and also improves the reliability of PZT capacitors used in FRAM® memory and other microelectronic devices.

Abstract: A ferroelectric thin film capacitor and a method for producing the same wherein the capacitor dielectric includes multi-layered crystallographic textures. An integrated circuit device, such as a non-volatile memory device, includes at least one capacitor having a top and bottom electrode thereof and a ferroelectric dielectric layer therebetween. The ferroelectric dielectric layer comprises a first ferroelectric layer having a first crystallographic texture forming a main body of the dielectric layer and a second ferroelectric layer having a second differing crystallographic texture forming an interface layer between the main body and one of the top and bottom electrodes.

Abstract: A ferroelectric memory cell includes a ferroelectric capacitor including a bottom electrode, a ferroelectric layer formed on the bottom electrode and a top electrode formed on the ferroelectric layer, a high permittivity dielectric layer formed over the ferroelectric capacitor, wherein the high permittivity dielectric layer includes an encapsulation layer and completely covers the top electrode, and a local interconnect electrode formed on the encapsulation layer.

Abstract: A charge storage capacitor includes a bottom electrode, a dielectric layer formed on the bottom electrode, and a local interconnect electrode formed on the dielectric layer, wherein the dielectric layer is an encapsulation layer, and a ferroelectric memory cell includes the charge storage capacitor.

Abstract: A charge storage capacitor includes a bottom electrode, a dielectric layer formed on the bottom electrode, and a local interconnect electrode formed on the dielectric layer, wherein the dielectric layer is an encapsulation layer, and a ferroelectric memory cell includes the charge storage capacitor.

Abstract: A charge storage capacitor includes a bottom electrode, a dielectric layer formed on the bottom electrode, and a local interconnect electrode formed on the dielectric layer, wherein the dielectric layer is an encapsulation layer, and a ferroelectric memory cell includes the charge storage capacitor.

Abstract: A method for fabrication of ferroelectric capacitor elements of an integrated circuit includes steps of deposition of an electrically conductive bottom electrode layer, preferably made of a noble metal. The bottom electrode is covered with a layer of ferroelectric dielectric material. The ferroelectric dielectric is annealed with a first anneal prior to depositing a second electrode layer comprising a noble metal oxide. Deposition of the electrically conductive top electrode layer is followed by annealing the layer of ferroelectric dielectric material and the top electrode layer with a second anneal. The first and the second anneal are performed by rapid thermal annealing.

Abstract: A method for manufacturing a ferroelectric memory cell includes the steps of forming a bottom electrode layer on a substrate, forming a ferroelectric thin film layer on the bottom electrode layer, forming a top electrode on the ferroelectric thin film layer, forming an encapsulating layer on the top electrode, forming a contact hole through the encapsulating layer, and co-annealing the ferroelectric thin film layer and the top electrode after forming the contact hole.

Abstract: A ferroelectric memory cell includes a ferroelectric capacitor including a bottom electrode, a ferroelectric layer formed on the bottom electrode and a top electrode formed on the ferroelectric layer, a high permittivity dielectric layer formed over the ferroelectric capacitor, wherein the high permittivity dielectric layer includes an encapsulation layer and completely covers the top electrode, and a local interconnect electrode formed on the encapsulation layer.

Abstract: A multi-layer ferroelectric thin film includes a nucleation layer, a bulk layer, and an optional cap layer. A thin nucleation layer of a specific composition is implemented on a bottom electrode to optimize ferroelectric crystal orientation and is markedly different from the composition required in the bulk of a ferroelectric film. The bulk film utilizes the established nucleation layer as a foundation for its crystalline growth. A multi-step deposition process is implemented to achieve a desired composition profile. This method also allows for an optional third composition adjustment near the upper surface of the film to ensure compatibility with an upper electrode interface and to compensate for interactions resulting from subsequent processing.