Abstract: A system and method for remotely waking up a device connected to a local area network (LAN) is disclosed. A special data packet is disclosed wherein the destination address of the packet is embedded at least 16 consecutive times within the data field of the packet. When this particular type of packet is transmitted on the LAN, it is first decoded by the I/O subsystem of the device to determine whether or not it is a remote wake-up packet. After determining that the packet received is a remote wake-up packet, a wake-up enable line is activated thereby taking the system out of its low power mode, for providing further processing of future received packets.

Abstract: An apparatus and method for remote wake-up of an intended node within a data exchange system having interlinked networks (e.g., router-interlinked LAN's) is disclosed. A wake-up commanding format is disclosed wherein a sequence corresponding to the address of the intended node is embedded N consecutive times (e.g., at least 16 consecutive times) extensively through the respective data fields of one or more packets sent from a remote source node to the intended node. When this particular sequence is received by the intended node while the intended node is in a sleep mode, a wake-up operation is responsively initiated so that the sleeping node will awaken, at least for a time, to respond to future received packets.

Abstract: A system for relocating expansion cards within a personal computer is provided that eliminates the need for manually changing the address locations. By examining both the address and the data of I/O accesses, the system provides security against accidental reprogramming of the device. Through the use of this system, both hardware implementation and the time needed to execute the reprogramming operation is minimized.

Abstract: A system is provided for ensuring that a ethernet controller operates to optimize bus latency and central processing unit (CPU) utilization in a network environment when reviewing data packets. Through the efficient use of a plurality of buffer memories and a driver, the bus utilization in conjunction with the controller the system provides for the receipt and transfer of data packets from the ethernet controller during the latency period of the network. In so doing, the overall performance of the network is enhanced.

Abstract: A system is disclosed that allows a computer system within a network environment to determine whether a data packet is to be processed by a particular computer system. This is accomplished through an address matching scheme that provides for an LED indication that the computer is to utilize the data packet provided by the network. In so doing, the system provides more capability to the computers on a network to operate more efficiently.