Abstract: Defect analysis of a semiconductor die is enhanced in a manner that makes possible the viewing of spatial manifestations of the defect from virtually any angle. According to an example embodiment of the present invention, substrate is removed from a semiconductor die while simultaneously obtaining images of the portions of the die from which substrate is being removed. The images are taken at various points in the substrate removal process, recorded and combined together to form a three-dimensional image of selected portions of the die. The image is then used to view the selected portions, and the nature of one or more defects therein are analyzed.

Abstract: Apparatus for and methods of inspection using laser beam induced alteration are provided. In one aspect, an apparatus is provided that includes a laser scanning microscope for directing a laser beam at a circuit structure and a source for biasing and thereby establishing a power condition in the circuit structure. A detection circuit is provided for detecting a change in the power condition in response to illumination of the circuit structure by the laser beam and generating a first output signal based on the detected change. A signal processor is provided for processing the first output signal and generating a second output signal based thereon. A control system is operable to scan the laser beam according to a pattern that has a plurality of pixel locations, whereby the laser beam may be moved to a given pixel location and allowed to dwell there for a selected time before being moved to another pixel location.

Abstract: Various apparatus and methods for enhancing hot-electron luminescence in an integrated circuit are provided. In one aspect, an apparatus is provided that includes a first circuit device coupled to a first voltage source that is operable to bias the first circuit device to a first voltage, and a second circuit device that has a first input coupled to the first voltage source and a junction defining a first side and a second side. One of the first and second sides is coupled to a second voltage source that is independent of the first voltage source and capable of selectively biasing the one of the first and second sides at a second voltage higher than the first voltage. The second device is operable to emit a hot-electron induced photon upon entry into saturation.

Abstract: The present invention is directed to the repair of resistive circuitry in an integrated circuit die having a multitude of circuit paths. According to an example embodiment of the present invention, a semiconductor die having a resistive electrical connection is analyzed. The location of a circuit portion in the die having a resistive electrical connection is identified. Using the identified location, the resistive circuit portion is annealed and the resistivity of that circuit portion is reduced. The reduced resistivity improves the ability of the die to operate at high speeds, and makes possible the repair and subsequent use of the die in various applications.

Abstract: A semiconductor apparatus includes a semiconductor body in the form of a silicon substrate havng a plurality of active devices. A metal stack including a plurality of metal layers is operatively associated with the active devices. A plurality of conductive elements are connected to the metal stack and to a substrate in the form of for example a printed circuit board. Vias connect conductive elements with respective portions of at least some of the metal layers, with the conductive elements connected to heat absorbing members within the substrate, which is in turn connected to a heat sink external to the substrate, the vias being spaced at regular intervals so as to promote heat dissipation from the metal stack therethrough to the heat absoring members and the heat sink.

Abstract: Integrated circuit devices are analyzed using an integrated system adapted to obtain time-resolved information from the back side of a silicon based semiconductor chip using hot carrier emissions. According to an example embodiment of the present invention, a system is adapted to analyze a semiconductor device under test (DUT) using a plurality of sensors mounted to a microscope having an objective lens. The plurality of sensors include a global acquisition sensor, a single-point acquisition sensor, and a navigation sensor. The integrated system is adapted to use the plurality of sensors individually and simultaneously. The integrated system improves the analysis of the DUT for reasons including that it makes possible the performance of more than one type of analysis simultaneously using a single test arrangement.

Abstract: The ability to monitor virtually any portion of semiconductor device is enhanced via a grid formed for analyzing circuitry in the semiconductor device. According to an example embodiment of the present invention, a grid having a plurality of narrow probe points is formed extending over target circuitry in a semiconductor device. The grid is accessed and used for monitoring various target circuitry within the device by accessing the part of the grid that corresponds to the portion of the target circuitry to which access is desired.

Abstract: According to one aspect of the disclosure and a particular example application directed to a flip-chip packaged die, a method for acquiring a signal from a target node in the circuit side includes removing substrate via the back side of the die to form an access area over the target node. A material is deposited in the access area over the target node in such a way to form simultaneously a conductive core and an immediately adjacent insulator. The conductive core is then used to couple a test signal between the target node and the conductive core. Other aspects of the disclosure include using a focused ion-beam system to provide varying concentrations of Gallium in forming simultaneously the conductive core and the immediately adjacent insulator. These aspects significantly lessen integrated circuit analysis and testing procedures.

Abstract: The ability to excite virtually any portion of semiconductor device is enhanced via a grid formed for exciting circuitry in the semiconductor device. According to an example embodiment of the present invention, a grid having a plurality of narrow probe points is formed extending over target circuitry in a semiconductor device. The grid is accessed and used for exciting various target circuitry within the device by exciting the part of the grid that corresponds to the portion of the target circuitry to which access is desired.

Abstract: A system for determining the endpoint associated with removing silicon from the backside of a flip chip type die includes a tool for removing silicon and a light source for directing light to the backside of the die. An electrical measuring apparatus, such as a voltmeter, ammeter or oscilloscope, is attached across the output pins of a package to which the die is attached. The light or ions directed toward the backside of the die induce a current in the devices formed in the semiconductor. The value of the current or voltage output depends on the thickness of material between the endpoint on the backside of the die and the devices in the epitaxial layer of the die. The induced signal can be monitored to determine the thickness. Silicon can be removed globally until the thickness is reasonable such that a local thinning tool can be used to remove silicon to get to the area of interest in a reasonable amount of time. The induced current can be monitored during local thinning.

Abstract: A method for bringing up lower level metal nodes of multi-layered IC devices (200) includes a step of boring a passage (210) down through the obstructing or non-target metal layers (220) exposing these layers, through the Inter Layer Dielectric layers (230), stopping at the target metal layer (240), and a step of depositing Gallium implanted insulator (250, 260) forming a node structure (280) with a conductive core (250) and an insulative sheath (260). The conductive core (250) brings up the target metal node or layer (240) and the insulative sheath (260) isolates the exposed non-target metal nodes or layers (220) from the target metal node (240) and the conductive core (250).

Abstract: A system for determining the endpoint associated with removing silicon from the backside of a flip chip type die includes a tool for removing silicon and a light source for directing light to the backside of the die. An electrical measuring apparatus, such as a voltmeter, ammeter or oscilloscope, is attached across the output pins of a package to which the die is attached. The light or ions directed toward the backside of the die induce a current in the devices formed in the semiconductor. The value of the current or voltage output depends on the thickness of material between the endpoint on the backside of the die and the devices in the epitaxial layer of the die. The induced signal can be monitored to determine the thickness. Silicon can be removed globally until the thickness is reasonable such that a local thinning tool can be used to remove silicon to get to the area of interest in a reasonable amount of time. The induced current can be monitored during local thinning.

Abstract: A method of precisely measuring electrical parameters in integrated circuits in a face down semiconductor device in which a portion of the semiconductor substrate is removed from the semiconductor device and an SEM microprobe is directed onto selected regions of the surface exposed by the removal of the semiconductor substrate. The microprobe is directed to selected regions of the exposed surface by a computer generated mapping system. One of the selected regions that the microprobe is directed to is a region of the exposed surface overlying a depletion region associated with a drain of a transistor in the semiconductor device. The voltage variation on the exposed surface caused by the expansion and shrinking of the depletion region is measured by the microprobe. Another region that the microprobe is directed to is a region of the exposed surface overlying an insulator and the microprobe detects the voltage of a conducting electrode under the insulator is measured via capacitive coupling.

Abstract: A protective circuit for bipolar integrated circuits to prevent inadvertent damage caused by electrostatic discharge includes a plurality of clamping networks (12a-12n). Each of the plurality of clamping networks (12a-12n). is connected between a corresponding one of a number of external input/output pins (P1-Pn) of the integrated circuit and a common bus line (14) which is connected to an external substrate pin (PS). Each of the plurality of clamping networks (12a-12n) includes a silicon-controlled rectifier (T1), a diode (D1), a first resistor (R1) and a second resistor (R2). When any one of the number of external input/output pins (P1-Pn) receives a voltage higher than a predeter-mined value and any remaining one of the external input/output pins (P1-Pn) contacts a ground potential, a discharge path is formed by a single silicon-controlled rectifier and a single diode so as to protect an internal circuit portion.

Abstract: A protection system for CMOS integrated circuits to prevent inadvertent damage caused by electrostatic discharge includes a low impedance power supply bus structure and a plurality of bipolar and MOS clamping networks. The bipolar clamping networks are formed around each of the bonding pads for interlinking all of them together through the low impendance power supply bus structure. When any one of the bonding pads receives a higher voltage than a predetermined value and another remaining one of the bonding pads contacts a ground potential, current is routed from the one bonding pad through the low impedance power supply bus structure to the other bonding pad in order to discharge the same.