Patents by Inventor Glen Gomes

Glen Gomes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7437588
    Abstract: Precise timing control within a standardized chassis such as PXI is obtained by providing several control signals over PXI_LOCAL. A Least Common Multiple (LCM) signal enables all clocks to have coincident clock edges occurring at every LCM edge. A start sequence allows all PXI expansion cards in the test system to start at the same time. A MATCH line enables pincard modules to check for expected DUT outputs and either continue execution of their local test programs or loop back and repeat a section of the local test program in accordance with the result of the DUT output check. An End Of Test (EOT) line enables any one pincard module to abruptly end the local test programs running in all other pincard modules if an error is detected by the local test program in the pincard module.
    Type: Grant
    Filed: August 3, 2005
    Date of Patent: October 14, 2008
    Assignee: Advantest Corporation
    Inventors: Anthony Le, Glen Gomes
  • Patent number: 7437589
    Abstract: Precise timing control within a standardized chassis such as PXI is obtained by providing several control signals over PXI_LOCAL. A Least Common Multiple (LCM) signal enables all clocks to have coincident clock edges occurring at every LCM edge. A start sequence allows all PXI expansion cards in the test system to start at the same time. A MATCH line enables pincard modules to check for expected DUT outputs and either continue execution of their local test programs or loop back and repeat a section of the local test program in accordance with the result of the DUT output check. An End Of Test (EOT) line enables any one pincard module to abruptly end the local test programs running in all other pincard modules if an error is detected by the local test program in the pincard module.
    Type: Grant
    Filed: August 3, 2005
    Date of Patent: October 14, 2008
    Assignee: Advantest Corporation
    Inventors: Anthony Le, Glen Gomes
  • Patent number: 7366939
    Abstract: Precise timing control across multiple standardized chassis such as PXI is obtained by providing several control signals over PXI_LOCAL within each chassis, and by providing these control signals to other chassis. A Least Common Multiple (LCM) signal enables all clocks to have coincident clock edges occurring at every LCM edge. A start sequence allows all PXI expansion cards in the test system to start at the same time. A MATCH line enables pincard modules to check for expected DUT outputs and either continue execution of their local test programs or loop back and repeat a section of the local test program in accordance with the result of the DUT output check. An End Of Test (EOT) line enables any one pincard module to abruptly end the local test programs running in all other pincard modules if an error is detected by the local test program in the pincard module.
    Type: Grant
    Filed: August 3, 2005
    Date of Patent: April 29, 2008
    Assignee: Advantest Corporation
    Inventors: Anthony Le, Glen Gomes
  • Publication number: 20070168766
    Abstract: Precise timing control across multiple standardized chassis such as PXI is obtained by providing several control signals over PXI_LOCAL within each chassis, and by providing these control signals to other chassis. A Least Common Multiple (LCM) signal enables all clocks to have coincident clock edges occurring at every LCM edge. A start sequence allows all PXI expansion cards in the test system to start at the same time. A MATCH line enables pincard modules to check for expected DUT outputs and either continue execution of their local test programs or loop back and repeat a section of the local test program in accordance with the result of the DUT output check. An End Of Test (EOT) line enables any one pincard module to abruptly end the local test programs running in all other pincard modules if an error is detected by the local test program in the pincard module.
    Type: Application
    Filed: August 3, 2005
    Publication date: July 19, 2007
    Applicant: Advantest Corporation
    Inventors: Anthony Le, Glen Gomes
  • Publication number: 20070043990
    Abstract: Precise timing control within a standardized chassis such as PXI is obtained by providing several control signals over PXI_LOCAL. A Least Common Multiple (LCM) signal enables all clocks to have coincident clock edges occurring at every LCM edge. A start sequence allows all PXI expansion cards in the test system to start at the same time. A MATCH line enables pincard modules to check for expected DUT outputs and either continue execution of their local test programs or loop back and repeat a section of the local test program in accordance with the result of the DUT output check. An End Of Test (EOT) line enables any one pincard module to abruptly end the local test programs running in all other pincard modules if an error is detected by the local test program in the pincard module.
    Type: Application
    Filed: August 3, 2005
    Publication date: February 22, 2007
    Applicant: Advantest Corporation
    Inventors: Anthony Le, Glen Gomes
  • Publication number: 20070040564
    Abstract: Precise timing control within a standardized chassis such as PXI is obtained by providing several control signals over PXI_LOCAL. A Least Common Multiple (LCM) signal enables all clocks to have coincident clock edges occurring at every LCM edge. A start sequence allows all PXI expansion cards in the test system to start at the same time. A MATCH line enables pincard modules to check for expected DUT outputs and either continue execution of their local test programs or loop back and repeat a section of the local test program in accordance with the result of the DUT output check. An End Of Test (EOT) line enables any one pincard module to abruptly end the local test programs running in all other pincard modules if an error is detected by the local test program in the pincard module.
    Type: Application
    Filed: August 3, 2005
    Publication date: February 22, 2007
    Applicant: Advantest Corporation
    Inventors: Anthony Le, Glen Gomes
  • Patent number: 7171602
    Abstract: An apparatus and method for computing event timing for high speed event based test system. The event processing apparatus includes an event memory for storing event data of each event where the event data includes timing data for each event which is formed with an integer multiple of a clock period and a fraction of the clock period, an event summing logic for accumulating the timing data and producing the accumulated timing data in a parallel form, and an event generator for generating events specified by the event data based on the accumulated timing data received in the parallel form from the event summing logic. The events in the event data are specified as groups of events where each group of event is configured by one base event and at least one companion event.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: January 30, 2007
    Assignee: Advantest Corp.
    Inventors: Glen Gomes, Anthony Le
  • Patent number: 7010452
    Abstract: An event pipeline and vernier summing apparatus for high speed event based test system processes the event data to generate drive events and strobe events with various timings at high speed to evaluate a semiconductor device under test. The event pipeline and vernier summing apparatus is configured by an event count delay logic, a vernier data decompression logic, an event vernier summation logic, an event scaling logic, and a window strobe logic. The event pipeline and summing method and apparatus of the present invention is designed to perform high speed event timing processing with use of a pipeline structure. The window strobe logic provides a function for detecting a window strobe request and generating a window strobe enable.
    Type: Grant
    Filed: July 12, 2003
    Date of Patent: March 7, 2006
    Assignee: Advantest Corp.
    Inventors: Glen Gomes, Anthony Le
  • Publication number: 20040107058
    Abstract: An event pipeline and vernier summing apparatus for high speed event based test system processes the event data to generate drive events and strobe events with various timings at high speed to evaluate a semiconductor device under test. The event pipeline and vernier summing apparatus is configured by an event count delay logic, a vernier data decompression logic, an event vernier summation logic, an event scaling logic, and a window strobe logic. The event pipeline and summing method and apparatus of the present invention is designed to perform high speed event timing processing with use of a pipeline structure. The window strobe logic provides a unique means for detecting a window strobe request and generating a window strobe enable.
    Type: Application
    Filed: July 12, 2003
    Publication date: June 3, 2004
    Inventors: Glen Gomes, Anthony Le
  • Publication number: 20030229473
    Abstract: An apparatus and method for computing event timing for high speed event based test system. The event processing apparatus includes an event memory for storing event data of each event where the event data includes timing data for each event which is formed with an integer multiple of a clock period and a fraction of the clock period, an event summing logic for accumulating the timing data and producing the accumulated timing data in a parallel form, and an event generator for generating events specified by the event data based on the accumulated timing data received in the parallel form from the event summing logic.
    Type: Application
    Filed: December 13, 2002
    Publication date: December 11, 2003
    Inventors: Glen Gomes, Anthony Le