Abstract: In a first aspect, a first method is provided for managing system resource allocation. The first method includes the steps of (1) receiving a first command that requires a system resource; (2) receiving a first request for the system resource for the first command; (3) receiving a second command that requires the system resource; (4) assigning the system resource to the second command; and (5) receiving a second request for the system resource for the second command. Numerous other aspects are provided.

Abstract: In a first aspect of the invention, a first method is provided for hierarchical scheduling. The first method includes the steps of (1) receiving data from one or more pipes, each pipe including a plurality of pipe flows (2) selecting a winning pipe from the one or more pipes from which to transmit data based upon one or more quality of service parameters corresponding to the winning pipe (3) selecting a pipe flow from the plurality of pipe flows included in the winning pipe based upon one or more quality of service parameters corresponding to the selected pipe flow and (4) transmitting data from the selected pipe flow. Numerous other aspects are provided.

Abstract: Systems, methods and computer program products for hardware assists for microcoded floating point divide and square root operations. Exemplary embodiments include a method including receiving a first microcoded instruction in the pipeline, decoding the first microcoded instruction in a decode stage of the pipeline, initiating a microcode engine coupled to the processor, with the microcode engine configured to process the streamlined microcode routine.

Abstract: Processor logic gates are used to modify microcode instructions, while they are being executed. The results of previous operations are used by the hardware to modify subsequent instructions in a microcode routine. This gives the effect of branching and also reduces the number of instructions that are executed. Different examples and embodiments are also discussed.

Abstract: In a first aspect, a first method of reissuing a command involving bus access is provided. The first method includes the steps of (1) storing information associated with commands that are to be reissued, wherein the commands are each associated with respective input/output (I/O) devices seeking bus access; (2) storing a count for each of the commands, each count indicating a number of times the associated command has been reissued; (3) selecting a command to be reissued, from among the commands, based on the information associated with the command; and (4) determining a delay after which the selected command will be reissued, wherein the delay is determined based on the count associated with the selected command. Numerous other aspects are provided.

Abstract: In a first aspect, a method is provided for scheduling connections for a network processor. The method includes the steps of, in a cache, scheduling a plurality of connections to be serviced based on quality of service parameters stored in a control structure corresponding to each connection and during a scheduling opportunity (1) identifying one or more of the plurality of connections in the cache to be serviced; (2) selecting one of the connections identified to be serviced; (3) servicing the selected connection; (4) accessing one or more portions of the control structure in the cache; (5) calculating a next service time when the selected connection is to be serviced; and (6) determining whether to schedule the selected connection to be serviced in one of the cache and a calendar based on the next service time. Numerous other aspects are provided.

Abstract: Systems, methods and computer program products for hardware assists for microcoded floating point divide and square root operations. Exemplary embodiments include a method including receiving a first microcoded instruction in the pipeline, decoding the first microcoded instruction in a decode stage of the pipeline, initiating a microcode engine coupled to the processor, with the microcode engine configured to process the streamlined microcode routine.

Abstract: A method and apparatus for register renaming in a computer system are provided. A map table stores physical register addresses corresponding to architected register addresses. An aritmetic available queue stores addresses of physical register available for aritmetic. A load available queue stores addresses of physical register available for loads. A store queue stores a plurality of pending physical store addresses. An aritmetic store compare function compares a displaced physical register address with the plurality of store addresses for updating the aritmetic available queue. A load store compare function compares a freed physical register address with the plurality of store addresses for updating the load available queue. An instruction queue stores a plurality of pending source and target instruction addresses.

Abstract: In a hardware floating point adder, each operand exponent is logically divided into fields. The corresponding fields of each exponent are input to a separate shift logic circuit which determines a relative amount to shift the operand mantissa without reference to any carry bit from a lower order field. Both mantissas are potentially shifted, each by one or more shift logic circuit outputs, making it possible to perform some of the shifts simultaneously. Using 11 bit exponents in accordance with ANSI/IEEE Standard 754-1985, double format for 64-bit numbers, operand registers are logically divided into: field #3, consisting the lowest two order bits; field #2 consisting of the next lowest two order bits after the first two; and field #1 consisting of the highest 7 order bits. The shift logic circuit for field #3 shifts and Operand A mantissa, right or left, 0, 1, 2 or 3 bits. The shift logic circuit for field #2 simultaneously shifts an Operand B mantissa, right or left, 0, 4, 8 or 12 bits.