Patents by Inventor Glen H. WALTERS

Glen H. WALTERS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240098969
    Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes formed in tiers. And, more particularly, to multiple, alternating silicon germanium (SiGe) and single crystalline silicon (Si) in different thicknesses to form tiers in which to form the horizontal access devices in vertical three-dimensional (3D) memory. The horizontally oriented access devices can have a first source/drain regions and a second source drain regions separated by single crystalline silicon (Si) channel regions. The single crystalline silicon (Si) channel regions can include a dielectric material to provide support structure to the single crystalline channel regions when forming the horizontal access devices in vertical three-dimensional (3D) memory. Horizontally oriented access lines can connect to gate structures opposing the channel regions. Vertical digit lines coupled to the first source/drain regions.
    Type: Application
    Filed: September 15, 2022
    Publication date: March 21, 2024
    Inventors: David K. Hwang, Yoshitaka Nakamura, Scott E. Sills, Si-Woo Lee, Yuanzhi Ma, Glen H. Walters
  • Publication number: 20240098970
    Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. The horizontally oriented access devices having a first source/drain regions and a second source drain regions separated by silicon (Si) channel regions. A digit line having a global digit line (GDL) contact is formed in a trench adjacent to the first source/drain regions. In one example, the digit line is electrically isolated from a neighboring digit line at the bottom of the trench. In another example, the digit line is formed continuously along a bottom surface of trench to form shared digit lines between horizontal access devices, in two separate arrays, on opposing second vertical surfaces. The memory cells have horizontally oriented storage nodes coupled to the second source/drain regions and vertical digit lines coupled to the first source/drain regions.
    Type: Application
    Filed: September 16, 2022
    Publication date: March 21, 2024
    Inventors: Scott E. Sills, Si-Woo Lee, David K. Hwang, Yoshitaka Nakamura, Yuanzhi Ma, Glen H. Walters
  • Publication number: 20230397391
    Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. The horizontally oriented access devices having a first source/drain regions and a second source drain regions separated by epitaxially grown, single crystalline silicon (Si) channel regions. A support structure is provided to the epitaxially grown, single crystalline Si. Horizontally oriented access lines connect to gates opposing the channel regions formed fully around every surface of the channel region as gate all around (GAA) structures separated from the channel regions by gate dielectrics. The memory cells have horizontally oriented storage nodes coupled to the second source/drain regions and vertical digit lines coupled to the first source/drain regions.
    Type: Application
    Filed: August 15, 2022
    Publication date: December 7, 2023
    Inventors: Si-Woo Lee, Scott E. Sills, David K. Hwang, Yoshitaka Nakamura, Yuanzhi Ma, Glen H. Walters
  • Publication number: 20230397390
    Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes formed in tiers. And, more particularly, to multiple, alternating epitaxially grown silicon germanium (SiGe) and single crystalline silicon (Si) in different thicknesses to form tiers in which to form the horizontal access devices in vertical three dimensional (3D) memory. The horizontally oriented access devices can have a first source/drain regions and a second source drain regions separated by epitaxially grown, single crystalline silicon (Si) channel regions. Horizontally oriented access lines can connect to gate all around (GAA) structures opposing the channel regions. Vertical digit lines coupled to the first source/drain regions.
    Type: Application
    Filed: August 15, 2022
    Publication date: December 7, 2023
    Inventors: David K. Hwang, John F. Kaeding, Matthew S. Thorum, Yuanzhi Ma, Scott E. Sills, Si-Woo Lee, Yoshitaka Nakamura, Glen H. Walters
  • Patent number: 11424271
    Abstract: Various examples are provided related to hydrogen plasma treatment of hafnium oxide. In one example, a method includes depositing a monolayer of a precursor on a first oxide monolayer; forming a second oxide monolayer by applying an oxygen (O2) plasma to the monolayer of the precursor; and creating oxygen vacancies in the second oxide monolayer by applying a hydrogen (H2) plasma to the second oxide monolayer. In another example, a device includes a hafnium oxide (HfO2) based ferroelectric thin film on a first side of a substrate and an electrode layer disposed on the HfO2 based ferroelectric thin film opposite the substrate. The HfO2 film includes a plurality of oxide monolayers including at least one HfO2 monolayer, each of the plurality of oxide monolayers having oxygen vacancies distributed throughout that oxide monolayer.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: August 23, 2022
    Assignee: UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INC.
    Inventors: Toshikazu Nishida, Saeed Moghaddam, Glen H. Walters, Aniruddh Shekhawat
  • Patent number: 11393973
    Abstract: A nano-mechanical acoustical resonator is designed and fabricated with CMOS compatible techniques to apply to mm-wave RF front-ends and 5G wireless communication systems which have extreme small scale and integrated in 3D sensors and actuators.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: July 19, 2022
    Assignee: University of Florida Research Foundation, Incorporated
    Inventors: Mayur Ghatge, Glen H. Walters, Toshikazu Nishida, Roozbeh Tabrizian
  • Publication number: 20220102384
    Abstract: Systems, methods, and apparatuses are provided for epitaxial single crystalline silicon growth for memory arrays. One example method includes forming logic circuitry on a silicon substrate in a first working surface and depositing an isolation material on the first working surface to encapsulate the logic circuitry and to form a second working surface above the first working surface. Further, the example method includes etching the isolation material to form a vertical opening through the isolation material and epitaxially growing single crystalline silicon from the silicon substrate and horizontally on the second working surface in a first, a second, and a third direction to cover the second working surface. The example method further includes removing a portion of the epitaxially grown single crystalline silicon to partition distinct and separate third working surface areas in which to form memory cell components and forming storage nodes above the memory cell components.
    Type: Application
    Filed: September 2, 2021
    Publication date: March 31, 2022
    Inventors: Glen H. Walters, John A. Smythe III, Scott E. Sills, John F. Kaeding
  • Publication number: 20210057455
    Abstract: Various examples are provided related to hydrogen plasma treatment of hafnium oxide. In one example, a method includes depositing a monolayer of a precursor on a first oxide monolayer; forming a second oxide monolayer by applying an oxygen (O2) plasma to the monolayer of the precursor; and creating oxygen vacancies in the second oxide monolayer by applying a hydrogen (H2) plasma to the second oxide monolayer. In another example, a device includes a hafnium oxide (HfO2) based ferroelectric thin film on a first side of a substrate and an electrode layer disposed on the HfO2 based ferroelectric thin film opposite the substrate. The HfO2 film includes a plurality of oxide monolayers including at least one HfO2 monolayer, each of the plurality of oxide monolayers having oxygen vacancies distributed throughout that oxide monolayer.
    Type: Application
    Filed: August 20, 2020
    Publication date: February 25, 2021
    Inventors: Toshikazu Nishida, Saeed Moghaddam, Glen H. Walters, Aniruddh Shekhawat
  • Publication number: 20200177152
    Abstract: A nano-mechanical acoustical resonator is designed and fabricated with CMOS compatible techniques to apply to mm-wave RF front-ends and 5G wireless communication systems which have extreme small scale and integrated in 3D sensors and actuators. Thin hafnium zirconium oxide (HZO) films are engineered with atomic layer deposition (ALD) to demonstrate large piezoelectric ferroelectric properties (piezoelectric coefficient e31,HZO?23e31,AlN. Various electrical and optical characterization schemes are also used as test-vehicles to characterize ferroelectric and piezoelectric properties, including isolated 10 nm HZO- and 120 nm AlN-transduction ports. The low-temperature and truly conformal nature of ALD process of HZO offers substantial advantages over conventional magnetronsputtered/MOCVD films, including CMOS-compatibility and sidewall transducer integration.
    Type: Application
    Filed: November 22, 2019
    Publication date: June 4, 2020
    Inventors: Mayur GHATGE, Glen H. WALTERS, Toshikazu NISHIDA, Roozbeh TABRIZIAN