Patents by Inventor Glen R. Anderson

Glen R. Anderson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for logic synthesis (word oriented netlist)
    Patent number: 6574787
    Abstract: An embodiment of the present invention is a method for logic synthesis that reduces use of computer memory and reduces computer runtime. In particular, an embodiment of the present invention is a method for logic synthesis which includes the steps of: (a) analyzing an HDL model to develop a parse tree and (b) elaborating the parse tree to create a word-oriented netlist.
    Type: Grant
    Filed: August 16, 1999
    Date of Patent: June 3, 2003
    Assignee: Sequence Design, Inc.
    Inventor: Glen R. Anderson
  • Method and apparatus for logic synthesis with elaboration
    Patent number: 6519755
    Abstract: An embodiment of the present invention is a method for logic synthesis that reduces use of computer memory and reduces computer runtime. In particular, an embodiment of the present invention is a method for logic synthesis which includes the steps of: (a) analyzing an HDL model to develop a parse tree and (b) elaborating the parse tree to create a word-oriented netlist; wherein elaborating comprises word-oriented elaborating.
    Type: Grant
    Filed: August 16, 1999
    Date of Patent: February 11, 2003
    Assignee: Sequence Design, Inc.
    Inventor: Glen R. Anderson
  • Method and apparatus for logic synthesis (inferring complex components)
    Patent number: 6493648
    Abstract: An embodiment of the present invention is a method for logic synthesis that reduces use of computer memory and reduces computer runtime. In particular, an embodiment of the present invention is a method for logic synthesis which includes the steps of: (a) analyzing an HDL model to develop a parse tree; (b) elaborating the parse tree to create a word-oriented netlist; and (c) inferring complex components from the word-oriented netlist.
    Type: Grant
    Filed: August 16, 1999
    Date of Patent: December 10, 2002
    Assignee: Sequence Design, Inc.
    Inventor: Glen R. Anderson
  • Virtual address to physical address translation of pages with unknown and variable sizes
    Patent number: 5956756
    Abstract: A method and apparatus for translating a virtual address to a physical address. A virtual address to be translated has a virtual page offset and a virtual page number. The virtual address to be translated addresses a page of memory. The size of this page is unknown. There are L different possible page sizes where L is a positive integer greater than one. Each of the L different page sizes is selected to be a test page size and a test is performed. During the test, a pointer into a translation storage buffer is calculated. The pointer is calculated from the virtual address to be translated by assuming that the virtual address to be translated corresponds to a mapping of the test page size. The pointer points to a candidate translation table entry of the translation storage buffer. The candidate translation table entry has a candidate tag and candidate data.
    Type: Grant
    Filed: June 6, 1997
    Date of Patent: September 21, 1999
    Assignee: Sun Microsystems, Inc.
    Inventors: Yousef A. Khalidi, Glen R. Anderson, Stephen A. Chessin, Shing Ip Kong, Charles E. Narad, Madhusudhan Talluri
  • Virtual address to physical address translation cache that supports multiple page sizes
    Patent number: 5479627
    Abstract: A method and apparatus for translating a virtual address to a physical address. A virtual address to be translated has a virtual page offset and a virtual page number. The virtual address to be translated addresses a page of memory. The size of this page is unknown. There are L different possible page sizes where L is a positive integer greater than one. Each of the L different page sizes is selected to be a test page size and a test is performed. During the test, a pointer into a translation storage buffer is calculated. The pointer is calculated from the virtual address to be translated by assuming that the virtual address to be translated corresponds to a mapping of the test page size. The pointer points to a candidate translation table entry of the translation storage buffer. The candidate translation table entry has a candidate tag and candidate data.
    Type: Grant
    Filed: September 8, 1993
    Date of Patent: December 26, 1995
    Assignee: Sun Microsystems, Inc.
    Inventors: Yousef A. Khalidi, Glen R. Anderson, Stephen A. Chessin, Shing I. Kong, Charles E. Narad, Madhusudhan Talluri