Abstract: According to one or more embodiments, a network node for communicating with at least one radio unit is provided. The network node including processing circuitry configured to: determine at least one code frame characteristic of a non-linear grid, map in-phase and quadrature, I/Q, data to non-linear grid having a plurality of regions that correspond to a plurality of code words where a plurality of bit sizes of the plurality of code words is a function of a radial distance from an origin of the non-linear grid, select a subset of the plurality of code words based at least in part on a target data rate for transmission, and cause transmission of the I/Q data based at least in part on the selected subset of the plurality of code words.

Abstract: A variable delay interface configured to introduce a controllable, variable delay between a radio equipment controller and a radio equipment is provided. The interface includes a variable rate change filter, VRCF, having a signal input, a signal output and a rate control input. The VRCF is configured to receive a rate control signal at the rate control inputs and sample an input signal received at the signal input at a sampling rate controlled by a rate control signal to produce a VRCF output signal. The sampling rate is one of greater than and less than a sampling rate of the input signal. The VRCF has a first delay. The interface includes a first in first out, FIFO, buffer having an input and an output, the FIFO buffer configured to store samples of the VRCF output signal received at the FIFO buffer.

Abstract: A variable delay interface configured to introduce a controllable, variable delay between a radio equipment controller and a radio equipment is provided. The interface includes a variable rate change filter, VRCF, having a signal input, a signal output and a rate control input. The VRCF is configured to receive a rate control signal at the rate control inputs and sample an input signal received at the signal input at a sampling rate controlled by a rate control signal to produce a VRCF output signal. The sampling rate is one of greater than and less than a sampling rate of the input signal. The VRCF has a first delay. The interface includes a first in first out, FIFO, buffer having an input and an output, the FIFO buffer configured to store samples of the VRCF output signal received at the FIFO buffer.

Abstract: A radio system having multi-standard mixed mode radios is described. The mixed mode radios are used to support combining of digital baseband from a first and a second radio equipment controller. A primary clock associated with the first radio equipment controller and a secondary clock associated with the second radio equipment controller is provided. The quality of the primary clock is evaluated and the primary clock is referenced to the first radio equipment controller if the clock is determined to have appropriate quality factors. The quality of the secondary clock is then evaluated and the secondary clock is referenced to the second radio equipment controller if the secondary clock is determined to have appropriate quality factors. The second radio equipment controller is then referenced to the primary clock once the primary and secondary clocks are aligned.

Abstract: A radio system having multi-standard mixed mode radios is described. The mixed mode radios are used to support combining of digital baseband from a first and a second radio equipment controller. A primary clock associated with the first radio equipment controller and a secondary clock associated with the second radio equipment controller is provided. The quality of the primary clock is evaluated and the primary clock is referenced to the first radio equipment controller if the clock is determined to have appropriate quality factors. The quality of the secondary clock is then evaluated and the secondary clock is referenced to the second radio equipment controller if the secondary clock is determined to have appropriate quality factors. The second radio equipment controller is then referenced to the primary clock once the primary and secondary clocks are aligned.

Abstract: A method and an interface unit is provided to maintain timing synchronization between a first Radio Equipment Controller (REC) and a second REC operating with a multi-standard base station. The first REC receives a synchronization signal and synchronized data output is generated from the synchronization signal. A clock signal is then generated from the synchronized data output. At the second REC, the synchronized data output is received and a synchronization source is then reconstructed from the first clock signal. A timing and frequency component of a second clock signal is then aligned to that of the reconstructed synchronization source, such that the second REC can maintain synchronization with the first REC.

Abstract: A method of controlling radio link delay in a multi-standard wireless system having a first Radio Equipment Controller (REC) operating with a first radio standard interface and a second REC operating with a second radio standard interface is disclosed. A time delay between the first REC and a Radio Equipment (RE) and a time delay between the second REC and the RE is determined. When radio signal data from the first and second REC are received, they are stored into a memory. The stored radio signal data is then marked in accordance with the calculated time delay. The marked radio signal data from each REC is then multiplexed into a single radio signal timed according to a reference timing clock signal for transmission to the RE.

Abstract: A method and an interface unit is provided to maintain timing synchronization between a first Radio Equipment Controller (REC) and a second REC operating with a multi-standard base station. The first REC receives a synchronization signal and synchronized data output is generated from the synchronization signal. A clock signal is then generated from the synchronized data output. At the second REC, the synchronized data output is received and a synchronization source is then reconstructed from the first clock signal. A timing and frequency component of a second clock signal is then aligned to that of the reconstructed synchronization source, such that the second REC can maintain synchronization with the first REC.