Abstract: An apparatus and method for detecting data conflicts in a multiple processor computer system and for throttling processing of instructions in individual pipelines where data conflicts exist. The present invention comprises circuitry for detecting data conflict problems in a computer system. The circuit of the present invention comprises a plurality of registers associated with each processor in the system. The registers are used to store a range of elements to be written by the associated processor and a plurality of ranges of elements to be read by the associated processor. These ranges are then compared against data accesses by other processors in the computer system and where a data conflict exists, a circuit is provided for determining which processor will be allowed to continue processing and which processor will be prevented from continuing processing.

Abstract: An apparatus and method for detecting data conflicts in a computer system and for throttling execution of instructions where data conflicts exist. The present invention comprises circuitry for detecting data conflict problems in a computer system. The circuit of the present invention comprises a plurality of registers associated with each processor in the system. The registers are used to store a range of elements to be written by the associated processor and a plurality of ranges of elements to be read by the associated processor. These ranges are then compared against data accesses by other processors in the computer system and where a data conflict exists, a circuit is provided for determining which processor will be allowed to continue processing and which processor will be prevented from continuing processing. The circuitry ensures the processor completes processing of instructions in a logical manner giving expected results.

Abstract: The invention is a bidirectional transposition exchange sorter for performing two overlapped sort operations overlapped in time with input/output operations so as to consume zero time. The sorter operates on the basis of a stack of cells, each of which contains two item storage locations and a comparator. The cells are arranged in a sorter stack configuration with a shift register monitor for each cell and an extra shift register position at the top of the sorter stack and also at the bottom. The monitor carries an indication of the current transfer mode for the cell. Each sort is carried out as two semi-sorts, input and output, which semi-sorts are time overlapped with the input and output operations typical of sort operations in computers. A portion of the sort operation takes place during an input step, so as to result in a partial reconfiguration of an unordered sequence at the end of the input semi-sort.

Abstract: Complex logical mechanism, for simultaneously producing output signals related logically to a set of input signals, implemented in transfer gate pairs. The first transfer gate of each pair is connected generally in series and is controlled by conduction according to the signals applied. The second transfer gate of each pair shunts the output node of its related first transfer gate to ground, when enabled by a control signal complementary to the data pattern applied to the first transfer gate of the pair. This direct control of line voltages affirmatively drives the lines or affirmatively grounds the lines to eliminate back circuits.Carry propagation to higher order bit positions is along carry propagate lines, with series connected carry propagate first transfer gates. Order positions not having data values appropriate for carry propagation do not transmit carry values--these transfer gates are not controlled for conduction, but are nonetheless subject to possible back circuits.