Abstract: A system or method for offloading data operations to a field programmable gate array (FPGA), that includes loading, by the FPGA, a descriptor ring, performing a first lookup, in the descriptor ring, to identify a first descriptor entry, identifying, in the first descriptor entry, a first data operation, making a first determination that the first data operation is unavailable in any of a plurality of module slots of the FPGA, and based on the first determination, loading a first operation module, matching the first data operation, into a first swappable module slot of the plurality of module slots.

Abstract: An information handling system for compressing data includes multiple compression engines, a source data buffer to provide compression data to the compression engines, at least one destination data buffer to receive compressed data from the compression engines, and a compression engine driver. Each compression engine is configured to provide a different compression function. The compression engine driver directs each compression engine to compress data from the source data buffer, and retrieves select compressed data from a first one of the compression engines from the at least one destination data buffer. The selection is based upon a selection criterion.

Abstract: An information handling system includes a processor that detects a cache flush request of a memory device within the processor, and identifies multiple blocks of data within an address space associated with the cache flush request. The processor groups the multiple blocks of data into a single composite block of data, and compresses the composite block of data. The processor stores the compressed composite block of data, and stores metadata for the compressed composite block of data. The metadata includes information for both the composite block of data and information for each of the multiple blocks of data.

Abstract: An information handling system for compressing data includes a data storage device and a processor. The data storage device stores a dictionary and an uncompressed data block. The processor prepends the dictionary to the uncompressed data block, determines, from the uncompressed data block, a literal data string and a match data string where the match data string is a matching entry of the dictionary, and compresses the uncompressed data block into a compressed data block that includes the literal data string and an offset pointer that points to the matching entry.

Abstract: An information handling system includes a compression client, a memory, and a SDXI hardware module. The compression client issues a compression request for a block of data that is uncompressed. The memory has multiple storage locations identified by addresses, which include a source address and a destination address. The SDXI hardware module performs compression of the block of data to create compressed data of the block of data. The SDXI hardware module determines whether an amount of the compression of the block of data is less than a threshold amount of compression. In response to the amount of the compression being less than the threshold amount of compression, the SDXI hardware module disregards the compressed data of the block of data, and utilizes the uncompressed block of data in a source address. The SDXI hardware module updates metadata for the block of data to indicate that data returned to compression client is uncompressed.

Abstract: An information handling system for compressing data includes a data storage device and a processor. The data storage device stores a dictionary and an uncompressed data block. The processor prepends the dictionary to the uncompressed data block, determines, from the uncompressed data block, a literal data string and a match data string where the match data string is a matching entry of the dictionary, and compresses the uncompressed data block into a compressed data block that includes the literal data string and an offset pointer that points to the matching entry.

Abstract: An information handling system includes a processor that detects a cache flush request of a memory device within the processor, and identifies multiple blocks of data within an address space associated with the cache flush request. The processor groups the multiple blocks of data into a single composite block of data, and compresses the composite block of data. The processor stores the compressed composite block of data, and stores metadata for the compressed composite block of data. The metadata includes information for both the composite block of data and information for each of the multiple blocks of data.

Abstract: An information handling system includes a compression client, a memory, and a SDXI hardware module. The compression client issues a compression request for a block of data that is uncompressed. The memory has multiple storage locations identified by addresses, which include a source address and a destination address. The SDXI hardware module performs compression of the block of data to create compressed data of the block of data. The SDXI hardware module determines whether an amount of the compression of the block of data is less than a threshold amount of compression. In response to the amount of the compression being less than the threshold amount of compression, the SDXI hardware module disregards the compressed data of the block of data, and utilizes the uncompressed block of data in a source address. The SDXI hardware module updates metadata for the block of data to indicate that data returned to compression client is uncompressed.

Abstract: An information handling system for compressing data includes multiple compression engines, a source data buffer to provide compression data to the compression engines, at least one destination data buffer to receive compressed data from the compression engines, and a compression engine driver. Each compression engine is configured to provide a different compression function. The compression engine driver directs each compression engine to compress data from the source data buffer, and retrieves select compressed data from a first one of the compression engines from the at least one destination data buffer. The selection is based upon a selection criterion.

Abstract: An information handling system includes a processor and a hardware device. The hardware device includes a first engine to provide a first operation on data, and a second engine to provide a second operation on data. The processor provides a command to the hardware device. The command directs the first engine to perform the first operation on first data to create second data based upon the performance of the first operation on the first data, and directs the second engine to perform the second operation on the second data to create third data based upon the performance of the second operation on the second data in response to a completion signal. The hardware device is configured to provide the completion signal to the second engine when the performance of the first operation on the first data is completed.

Abstract: A mechanism for managing packetized data transfers in a system including a transmitting and a receiving device. The transmitting device may transmit data to the receiving device in a plurality of packets, each packet a predetermined number of data bytes wide. The transmitting device may include a transfer count unit to maintain a data transfer count based on a number of transmitted data bytes. The receiving device may program the transmitting device with a transfer count mark, which may be a number that corresponds to a specific count of the data transfer count. The transmitting device may calculate a difference between the data transfer count and the transfer count mark. If the difference between the transfer count and the transfer count mark is less than the predetermined number, the transmitting device may transmit a short data packet having less than the predetermined number of data bytes to the receiving device.

Abstract: A delay circuit. In one embodiment, a programmable logic device (PLD) is used to implement one or more delay circuits having a plurality of delay elements. Included in the plurality of elements are a balanced number of logic elements such that rising and falling edges of a signal passing through the delay circuit propagate with substantially the same amount of delay. The delay circuit may also include a selector circuit coupled to select an output from one of the plurality of delay elements. The delay circuit may be implemented such that it preserves the duty cycle and/or pulse width of signals to which the delay is applied.

Abstract: A system and method for transferring data over a communications medium. A host is coupled to a device through a serial bus lacking error handling capabilities, such as an IEEE 1394 bus. The host may control the device by sending requests accessing its memory registers. The host generates a first request to the device to access a memory address location of the device, and which includes an address and status information indicating whether a prior request to the memory address location returned successfully. The device examines the status information to determine if it is a retry of a prior request, and if so, determines if the prior request completed successfully to the memory address location by comparing the address and data transfer size of the first request to those of the prior request. If identical, then the prior request completed successfully to the memory address location, and the request is ignored. Otherwise, the device retries the prior request.

Abstract: A Wide Area Serial PCI system for connecting peripheral devices to a computer. The WASP system includes a host computer system connected through a serial bus to a remote device. The serial bus can range from several meters to several kilometers or more. The host computer system includes a CPU and memory, and also includes a first Peripheral Component Interconnect (PCI) bus, also referred to as the local PCI bus. A primary bridge according to the present invention is coupled to the first PCI bus. The primary bridge includes PCI interface circuitry for interfacing to the first PCI bus. The remote device is located remotely from the computer system and comprises a second or remote PCI bus and one or more peripheral devices coupled to the second PCI bus. The remote device also includes a secondary bridge coupled to the second PCI bus. The secondary bridge includes PCI interface circuitry for interfacing to the second PCI bus. The serial bus is coupled between the primary bridge and the secondary bridge.