Patents by Inventor Glen Wada
Glen Wada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6943071Abstract: A nonvolatile memory cell comprising a pair of spaced apart shallow trench isolation regions formed in a substrate and defining a substrate active region. A tunnel dielectric is formed on the substrate active region. A floating gate is formed on the tunnel dielectric and is self aligned between the spaced apart shallow trench isolation regions. A dielectric layer is formed on the floating gate and a control gate formed on the dielectric layer. A source region and a drain region are formed in the substrate active region on opposite sides of the floating gate.Type: GrantFiled: June 3, 2002Date of Patent: September 13, 2005Assignee: Intel CorporationInventors: Albert Fazio, Krishna Parat, Glen Wada, Neal Mielke, Rex Stone
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Patent number: 6849896Abstract: A method for making a flash memory having a passivation layer that is not transparent to ultraviolet light. The method forming a semiconductor that includes flash memory cell having floating gate, then forming a the substrate. Process induced charge that has accumulated on the flash cell floating gate is then neutralized and a passivation layer, which is no transparent to ultraviolet light, is formed on the conductive layer.Type: GrantFiled: November 9, 2001Date of Patent: February 1, 2005Assignee: Intel CorporationInventors: Glen Wada, Raghupathy V. Giridhar, Anthony Ozzello
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Patent number: 6518618Abstract: A nonvolatile memory cell comprising a pair of spaced apart shallow trench isolation regions formed in a substrate and defining a substrate active region. A tunnel dielectric is formed on the substrate active region. A floating gate is formed on the tunnel dielectric and is self aligned between the spaced apart shallow trench isolation regions. A dielectric layer is formed on the floating gate and a control gate formed on the dielectric layer. A source region and a drain region are formed in the substrate active region on opposite sides of the floating gate.Type: GrantFiled: December 3, 1999Date of Patent: February 11, 2003Assignee: Intel CorporationInventors: Albert Fazio, Krishna Parat, Glen Wada, Neal Mielke, Rex Stone
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Publication number: 20020149050Abstract: A nonvolatile memory cell comprising a pair of spaced apart shallow trench isolation regions formed in a substrate and defining a substrate active region. A tunnel dielectric is formed on the substrate active region. A floating gate is formed on the tunnel dielectric and is self aligned between the spaced apart shallow trench isolation regions. A dielectric layer is formed on the floating gate and a control gate formed on the dielectric layer. A source region and a drain region are formed in the substrate active region on opposite sides of the floating gate.Type: ApplicationFiled: June 3, 2002Publication date: October 17, 2002Inventors: Albert Fazio, Krishna Parat, Glen Wada, Neal Mielke, Rex Stone
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Publication number: 20020094595Abstract: A method for making a flash memory having a passivation layer that is not transparent to ultraviolet light. The method comprises forming a semiconductor substrate that includes a flash memory cell having a floating gate, then forming a conductive layer on the substrate. Process induced charge that has accumulated on the flash cell floating gate is then neutralized and a passivation layer, which is not transparent to ultraviolet light, is formed on the conductive layer.Type: ApplicationFiled: November 9, 2001Publication date: July 18, 2002Inventors: Glen Wada, R.V. Giridhar, Anthony Ozzello
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Patent number: 6365521Abstract: A method of passivating an integrated circuit comprising providing an integrated circuit having a top side including a bond pad, depositing a first dielectric over said top side of said integrated circuit, exposing a first area portion of a top side of said bond pad, depositing a second dielectric of one of a material that is substantially impermeable to moisture over said top side of said integrated circuit, and exposing a second area portion of said top side of said bond pad, said second area portion within said first area portion is disclosed.Type: GrantFiled: December 31, 1997Date of Patent: April 2, 2002Assignee: Intel CorporationInventors: Jan V. Shubert, Glen Wada, Mansour Moinpour, Yang-Chin Shih, Ken Schatz
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Patent number: 6350651Abstract: A method for making a flash memory having a passivation layer that is not transparent to ultraviolet light. The method comprises forming a semiconductor substrate that includes a flash memory cell having a floating gate, then forming a conductive layer on the substrate. Process induced charge that has accumulated on the flash cell floating gate is then neutralized and a passivation layer, which is not transparent to ultraviolet light, is formed on the conductive layer.Type: GrantFiled: June 10, 1999Date of Patent: February 26, 2002Assignee: Intel CorporationInventors: Glen Wada, R. V. Giridhar, Anthony Ozzello
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Publication number: 20010024857Abstract: A method of fabricating a flash memory integrated circuit is described. In an embodiment of the present invention a dielectric filled trench isolation region is formed in a silicon substrate. The dielectric filled trench isolation region isolates a first portion of the silicon substrate from a second portion of the silicon substrate. A portion of the dielectric in the trench is then removed to reveal a portion of the silicon substrate in the trench between the first and second portions of the silicon substrate. Ions are then implanted to form a first source region in the first portion of the silicon substrate and to form a second source region in the second portion of the silicon substrate and to form a doped region in the revealed silicon substrate in the trench wherein the doped region in the trench extends from the first doped source region to the second doped source region.Type: ApplicationFiled: May 23, 2001Publication date: September 27, 2001Inventors: Krishna Parat, Raghupathy V. Giridhar, Cheng C. Hu, Daniel Xu, Yudong Kim, Glen Wada
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Patent number: 6265292Abstract: A method of fabricating a flash memory integrated circuit is described. In an embodiment of the present invention a dielectric filled trench isolation region is formed in a silicon substrate. The dielectric filled trench isolation region isolates a first portion of the silicon substrate from a second portion of the silicon substrate. A portion of the dielectric in the trench is then removed to reveal a portion of the silicon substrate in the trench between the first and second portions of the silicon substrate. Ions are then implanted to form a first source region in the first portion of the silicon substrate and to form a second source region in the second portion of the silicon substrate and to form a doped region in the revealed silicon substrate in the trench wherein the doped region in the trench extends from the first doped source region to the second doped source region.Type: GrantFiled: July 12, 1999Date of Patent: July 24, 2001Assignee: Intel CorporationInventors: Krishna Parat, Raghupathy V. Giridhar, Cheng C. Hu, Daniel Xu, Yudong Kim, Glen Wada
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Patent number: 5758095Abstract: A system and method for ordering and prescribing drugs for a patient. This system includes an improved process for facilitating and automating the process of drug order entry. The user may interact with the system in a variety of ways such as keyboard, mouse, pen-base entry or voice entry. The system includes a database containing medical prescribing and drug information which is both general and patient-specific. The system also permits the user to view current and previously prescribed medications for any patient. The system can alert the user to potentially adverse situations as a result of the prescribed medication based on information in the database. The system also can automatically determine product selection based on descriptions and can automatically communicate the order to a pharmacy. Further, the system includes a means for automatically displaying messages to the user relating to predetermined situations.Type: GrantFiled: February 24, 1995Date of Patent: May 26, 1998Inventors: David Albaum, Jeff Inokuchi, Denis Kitayama, Glen Wada, Ray Wong, Brian Komoto
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Patent number: 4808259Abstract: A method for etching of metal-oxide-semiconductor (MOS) devices utilizing a multi-step power reduction plasma etching recipe to reduce ion bombardment damage on the resulting surface. The multi-step power reduction recipe allows for reasonable throughput of wafers due to a relatively high etch rate at the upper layers of the surface followed by progressively lower power corresponding lower etch rates at the lower levels of the surface. The etching process is followed by a cleaning process to remove metallic contamination resulting from the plasma etching process to yield an excellent surface for growing low defect density MOS gate oxides with high dielectric integrity.Type: GrantFiled: January 25, 1988Date of Patent: February 28, 1989Assignee: Intel CorporationInventors: Don W. Jillie, Jr., Gerald Yin, Glen Wada