Abstract: A method and apparatus for applying patches to a code or data residing on a non-volatile memory device is illustrated. A code residing at a first location in a non-volatile memory can be replaced by a codes residing at a second locations in a memory map. A patching device compares a first address of a first code to an address identified by a pre-fetch instruction. If the first address matches the address identified by the pre-fetch instruction, a pre-fetch abort is issued to facilitate replacing a bad code residing at the first address with a good code. The good code can be pointed to by a vector in a vector table where the address of the vector is dynamically loaded into a program counter.

Abstract: A method and apparatus for applying patches to a code or data residing on a non-volatile memory device is illustrated. A code residing at a first location in a non-volatile memory can be replaced by a codes residing at a second locations in a memory map. A patching device compares a first address of a first code to an address identified by a pre-fetch instruction. If the first address matches the address identified by the pre-fetch instruction, a pre-fetch abort is issued to facilitate replacing a bad code residing at the first address with a good code. The good code can be pointed to by a vector in a vector table where the address of the vector is dynamically loaded into a program counter.

Abstract: A data processing system (20) has a display controller (28) that uses bus arbitration and data bursting to supply display data for refreshing an LCD screen (49), utilizing a system memory (30) instead of a separate video RAM. A screen DMA (58) fills a line buffer (60) with display data from the system memory (30) in bursts of a predetermined number of words. The screen DMA (58) receives a faster clocking signal than is used by the CPU (22). This allows the screen DMA (58) to run faster than the CPU (22) to reduce bandwidth needed to retrieve the display data. In addition, if the CPU (22) clock frequency is changed for power management purposes, the LCD screen (49) is not affected since it uses a different clock. By using the system memory (30) for storing display data, pin count, packaging costs, and board space are reduced.

Abstract: A data processing system (20) has a multi-function scalable parallel I/O port (44). The I/O port (44) includes a plurality of I/O port circuits (55, 56) coupled to I/O terminals (67, 77) . The I/O port (44) can multiplex two functions onto one terminal (67,77) . One function is an I/O function and the other function is function under the control of an internal module (22, 24, 26, 32) connected to the terminal (67, 77). Each I/O port circuit (55, 56) has either a pull-down circuit (68) or a pull-up circuit (78) coupled to the terminal (67, 77). The pull-up and pull-down circuits (78, 68) are controllable using a control register (81, 82). The pull-up and pull-down circuits (78, 68) for each terminal (67, 77) can be individually selected, and function whether the I/O port (44) is selected or deselected.