Abstract: A TRIAC semiconductor includes an N? region, multiple N+ regions, and a trench. The N? region is sandwiched between two P regions. The first P region is connected to an MT2 terminal and the second P region is connected to two MT1 terminals. The multiple N+ regions are located within the first P region. The trench is located between two gate terminals.

Abstract: A semiconductor apparatus including first, second, and third silicon layers, the first silicon being coupled to the second silicon layer and the second silicon layer being coupled to the third silicon layer. The apparatus includes a trench formed in the first silicon layer and in at least a portion of the second silicon layer, an isolation region formed in at least the second silicon layer, where the isolation region extends from the trench to the third silicon layer. The apparatus also includes a first main terminal one and a first gate terminal coupled to a first portion of the first silicon layer, a second main terminal one and a second gate terminal coupled to a second portion of the first silicon layer, a main terminal two coupled to the third silicon layer, and one or more silicon regions in the first silicon layer and in the third silicon layer.

Abstract: A high power density rectifier diode apparatus, structure and associated methods thereof. The apparatus includes a substrate silicon layer, a middle silicon layer coupled to the substrate layer, an upper silicon layer coupled to the middle silicon layer, a cathode terminal coupled to the substrate silicon layer, an anode terminal coupled to the upper silicon layer, and one or more trench termination layers formed in the substrate silicon layer and at least a portion of the middle silicon layer. The trench termination layers are configured to be formed on at least one side of the substrate silicon layer and at least a portion of the middle silicon layer. The substrate silicon layer is at least one of the following: an n-type layer, a p-type layer, and any combination thereof.

Abstract: A silicon controlled rectifier includes a first P region, an N? region, a second P region, and a plurality of N+ regions. The first P region is connected to an anode. The N? region is adjacent the first P region. The second P region is adjacent the N? region such that the N? region is sandwiched between the first P region and the second P region. The plurality of N+ regions are disposed within the second P region. A first N+ region of the plurality of N+ regions is connected to a cathode. A second N+ region of the plurality of N+ regions is connected to a gate.

Abstract: A multiple-channel protection device and associated methods thereof. The device includes a first lead having a first chip attachment portion and a second chip attachment portion, a second lead having a third chip attachment portion, and a third lead having a fourth chip attachment portion. A first semiconductor chip is configured to be conductively coupled to the first chip attachment portion and the third chip attachment portion. A second semiconductor chip is configured to be conductively coupled to the second chip attachment portion and the fourth chip attachment portion.

Abstract: A TVS device may include a substrate, comprising a polarity of a first type, a first dopant layer, disposed on a first main surface of the substrate, and comprising a polarity of a second type, wherein the first dopant layer forms a P/N junction with the substrate. The TVS device may further include a second dopant layer, disposed on a second main surface of the substrate, opposite the first main surface, the second layer comprising the polarity of the first type, and a patterned layer, disposed on the second main surface of the substrate, the patterned layer comprising the polarity of the second type, wherein the patterned layer is interspersed with the second layer.

Abstract: An overvoltage protection device may include an n-type semiconductor substrate, a p-type layer disposed atop the n-type semiconductor substrate, and a passivation region formed in the n-type semiconductor substrate and the p-type layer, wherein the passivation region comprises a semi-insulating polycrystalline silicon (SIPOS) layer.

Abstract: Provided herein are package structures including a first lead frame having a first pedestal and a first lead extending from the first pedestal. A first perimeter ridge defines a first recessed area in a first main side of the first pedestal, wherein a die pad is positioned within the first recessed area. The package structure may further include a chip layer having a first main side opposite a second main side, wherein the second main side is in abutment with the first perimeter ridge of the pedestal of the first lead frame. The package structure may further include a clip including a second pedestal and a lead connector extending from the second pedestal, wherein a second perimeter ridge defines a second recessed area in a second main side of the second pedestal, and wherein the second perimeter ridge is in abutment with the first main side of the chip layer.