Abstract: An improved phase locked indication circuit for a Costas QPSK carrier recovery loop comprises an inphase channel, a quadrature channel and phase error channel each connected to an input of a three input summing circuit through a diode square law multiplier and wherein the error channel signal is filtered by a low pass filter to smooth the signal before being applied to the negative input of the summing circuit to diminish false lock and not locked signals. The locked and not lock conditions are separated one from the other by a large signal to noise ratio.

Abstract: An improved digital data modulator is provided for a digital transmitter. The digital data modulator comprises of a pair of digital data synthesizers which are controlled in a manner which produces complex conjugate modulated data signals of the input signals. Summing means are provided to sum the outputs of the digital data synthesizers in a manner which removes the imaginary components and simultaneously reduces the side load power without employing conventional filters.

Abstract: A bit synchronizing circuit is provided with both analog and digital devices in an enhanced bit synchronizing circuit system. There is provided a digital phase detector and a digital lock detector which are compatible with analog circuity. The output of the digital phase detector is coupled to an analog summing circuit having an output which is coupled to a low pass filter (LPF). The analog output of the LPF is coupled to the input of a voltage controlled oscillator (VCO) which produces a data rate clock. The output of the digital lock detector is coupled to an analog summing circuit having an output coupled to a low pass filter (LPF). The output of the LPF is coupled to a comparator for generating a lock indication signal output. The output of the comparator is also coupled to a sweep circuit which is coupled to an input of the voltage controlled oscillator for resolving frequency uncertainties in the bit synchronizing circuit.

Abstract: A novel high-speed bit synchronizer circuit comprises a phase detector having two phase detecting loops, each adapted to generate a partial error voltage signal which is summed together to provide a single phase voltage error signal which is employed to control a VCO in the return branch of both phase detecting loops. Each phase detecting loop comprises a comparator coupled to the input data stream and to a reference voltage to provide two outputs. An electronic switch is coupled to the output of each comparator and each switch has its partial error voltage output coupled through a summing circuit to the VCO, thus completing two phase detecting loops each adapted to generate a partial phase error signal indicative of the phase error between the input data stream and the recovered clock output of the VCO.

Abstract: Self-clocking system for demodulating phase encoded data automatically tracks incoming data rate changes by using information from a bit synchronizer to track the incoming base band data signal.

Abstract: The present invention provides a high frequency lock detecting circuit for generating a signal indicative of a locked or a not locked phase tracking condition in a phase locked loop circuit. The lock detector comprises a plurality of high speed function generators two of which are coupled to the modulated data streams for indicating the phase data streams and a third high speed function generator is coupled to the voltage error signal of the phase locked loop for indicating the absence or presence of a voltage error signal. The analog outputs of the function generators are summed together in a summing circuit and applied to a differential amplifier which removes the complex modulated data products from the output of the function generators and provides a signal which is equal to the absolute value of the data signals applied to the first function generators minus the absolute value of the error signal applied by the third function generator.