Patents by Inventor Glenn A. Dearth

Glenn A. Dearth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11082347
    Abstract: Multiple processors are often used in computing systems to solve very large, complex problems, such as those encountered in artificial intelligence. Such processors typically exchange data among each other via an interconnect fabric (such as, e.g., a group of network connections and switches) in solving such complex problems. The amount of data injected into the interconnect fabric by the processors can at times overwhelm the interconnect fabric preventing some of the processors from communicating with each other. To address this problem, techniques are disclosed to enable, for example, processors that are connected to an interconnect fabric to coordinate and control the amount of data injected so that the interconnect fabric does not get overwhelmed.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: August 3, 2021
    Assignee: Nvidia Corporation
    Inventors: Glenn Dearth, Nan Jiang, John Wortman, Alex Ishii, Mark Hummel, Rich Reeves
  • Patent number: 11038800
    Abstract: An endpoint in a network may make posted or non-posted write requests to another endpoint in the network. For a non-posted write request, the target endpoint provides a response to the requesting endpoint indicating that the write request has been serviced. For a posted write request, the target endpoint does not provide such an acknowledgment. Hence, posted write requests have lower overhead, but they suffer from potential synchronization and resiliency issues. While non-posted write requests do not have those issues, they cause increased load on the network because such requests require the target endpoint to acknowledge each write request. Introduced herein is a network operation technique that uses non-posted transactions while maintaining a load overhead of the network as a manageable level. The introduced technique reduces the load overhead of the non-posted write requests by collapsing and reducing a number of the responses.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: June 15, 2021
    Assignee: Nvidia Corporation
    Inventors: Glenn Dearth, Mark Hummel, Jonathan Owen, Mike Osborn, John Wortman, Rich Reeves
  • Publication number: 20210133123
    Abstract: Fabric Attached Memory (FAM) provides a pool of memory that can be accessed by one or more processors, such as a graphics processing unit(s) (GPU)(s), over a network fabric. In one instance, a technique is disclosed for using imperfect processors as memory controllers to allow memory, which is local to the imperfect processors, to be accessed by other processors as fabric attached memory. In another instance, memory address compaction is used within the fabric elements to fully utilize the available memory space.
    Type: Application
    Filed: November 4, 2019
    Publication date: May 6, 2021
    Inventors: John FEEHRER, Denis Foley, Mark Hummel, Vyas Venkataraman, Ram Gummadi, Samuel H. Duncan, Glenn Dearth, Brian Kelleher
  • Publication number: 20210067449
    Abstract: An endpoint in a network may make posted or non-posted write requests to another endpoint in the network. For a non-posted write request, the target endpoint provides a response to the requesting endpoint indicating that the write request has been serviced. For a posted write request, the target endpoint does not provide such an acknowledgment. Hence, posted write requests have lower overhead, but they suffer from potential synchronization and resiliency issues. While non-posted write requests do not have those issues, they cause increased load on the network because such requests require the target endpoint to acknowledge each write request. Introduced herein is a network operation technique that uses non-posted transactions while maintaining a load overhead of the network as a manageable level. The introduced technique reduces the load overhead of the non-posted write requests by collapsing and reducing a number of the responses.
    Type: Application
    Filed: August 28, 2019
    Publication date: March 4, 2021
    Inventors: Glenn Dearth, Mark Hummel, Jonathan Owen, Mike Osborn, John Wortman, Rich Reeves
  • Publication number: 20210014156
    Abstract: Introduced herein is a routing technique that, for example, routes a transaction to a destination port over a network that supports link aggregation and multi-port connection. In one embodiment, two tables that can be searched based on the target and supplemental routing IDs of the transaction are utilized to route the transaction to the proper port of the destination endpoint. In an embodiment, the first table provides a list of available ports at each hop/route point that can route the transaction to the destination endpoint, and the second table provides a supplemental routing ID that can select a specific group of ports from the first table that can correctly route the transaction to the proper port.
    Type: Application
    Filed: December 2, 2019
    Publication date: January 14, 2021
    Inventors: Glenn Dearth, Mark Hummel
  • Patent number: 10789194
    Abstract: Systems and techniques for synchronizing transactions between processing devices on an interconnection network are provided. Upon receiving a stream of posted transactions followed by a flush transaction from a source processing device connected to the interconnection network, the flush transaction is trapped before it enters the interconnecting network. Subsequently, based on monitoring for responses received from a destination processing device for transactions corresponding to the posted transactions, a flush response is generated and returned to the source processing device. The described techniques enable efficient synchronizing posted writes, posted atomics and the like over complex interconnection fabrics such that a first GPU can write data to a second GPU so that a third GPU can safely consume the data written to the second GPU.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: September 29, 2020
    Assignee: NVIDIA Corporation
    Inventors: Larry R. Dennison, Mark Hummel, Glenn Dearth
  • Publication number: 20190294575
    Abstract: Systems and techniques for synchronizing transactions between processing devices on an interconnection network are provided. Upon receiving a stream of posted transactions followed by a flush transaction from a source processing device connected to the interconnection network, the flush transaction is trapped before it enters the interconnecting network. Subsequently, based on monitoring for responses received from a destination processing device for transactions corresponding to the posted transactions, a flush response is generated and returned to the source processing device. The described techniques enable efficient synchronizing posted writes, posted atomics and the like over complex interconnection fabrics such that a first GPU can write data to a second GPU so that a third GPU can safely consume the data written to the second GPU.
    Type: Application
    Filed: March 26, 2019
    Publication date: September 26, 2019
    Inventors: Larry R. DENNISON, Mark HUMMEL, Glenn DEARTH
  • Publication number: 20190297018
    Abstract: Multiple processors are often used in computing systems to solve very large, complex problems, such as those encountered in artificial intelligence. Such processors typically exchange data among each other via an interconnect fabric (such as, e.g., a group of network connections and switches) in solving such complex problems. The amount of data injected into the interconnect fabric by the processors can at times overwhelm the interconnect fabric preventing some of the processors from communicating with each other. To address this problem, techniques are disclosed to enable, for example, processors that are connected to an interconnect fabric to coordinate and control the amount of data injected so that the interconnect fabric does not get overwhelmed.
    Type: Application
    Filed: February 15, 2019
    Publication date: September 26, 2019
    Inventors: Glenn Dearth, Nan Jiang, John Wortman, Alex Ishii, Mark Hummel, Rich Reeves
  • Patent number: 10275386
    Abstract: A plurality of registers implemented in association with a memory physical layer interface (PHY) can be used to store one or more instruction words that indicate one or more commands and one or more delays. A training engine implemented in the memory PHY can generate at-speed programmable sequences of commands for delivery to an external memory and to delay the commands based on the one or more delays. The at-speed programmable sequences of commands can be generated based on the one or more instruction words.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: April 30, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Glenn A. Dearth, Gerry Talbot
  • Patent number: 9851744
    Abstract: In one form, an apparatus comprises a delay circuit and a controller. The delay circuit delays a plurality of command and address signals according to a first delay signal and provides a delayed command and address signal to memory interface. The controller performs command and address training in which the controller provides an activation signal and a predetermined address signal with first timing according to the first delay signal, and the plurality of command and address signals besides the predetermined address signal with second timing according to the first delay signal, wherein the second timing is relaxed with respect to the first timing. The controller determines an eye of timing for the predetermined address signal by repetitively providing a predetermined command on the command and address signals, varying the first delay signal, and measuring a data signal received from the memory interface.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: December 26, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Glenn Dearth, Anwar Kashem, Sean Cummins
  • Patent number: 9639495
    Abstract: A controller integrated in a memory physical layer interface (PHY) can be used to control training used to configure the memory PHY for communication with an associated external memory such as a dynamic random access memory (DRAM), thereby removing the need to provide training sequences over a data pipeline between a BIOS and the memory PHY. For example, a controller integrated in the memory PHY can control read training and write training of the memory PHY for communication with the external memory based on a training algorithm. The training algorithm may be a seedless training algorithm that converges on a solution for a timing delay and a voltage offset between the memory PHY and the external memory without receiving, from a basic input/output system (BIOS), seed information that characterizes a signal path traversed by training sequences or commands generated by the training algorithm.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: May 2, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Glenn A. Dearth, Gerry Talbot, Anwar Kashem, Edoardo Prete, Brian Amick
  • Publication number: 20160172013
    Abstract: In one form, an apparatus comprises a delay circuit and a controller. The delay circuit delays a plurality of command and address signals according to a first delay signal and provides a delayed command and address signal to memory interface. The controller performs command and address training in which the controller provides an activation signal and a predetermined address signal with first timing according to the first delay signal, and the plurality of command and address signals besides the predetermined address signal with second timing according to the first delay signal, wherein the second timing is relaxed with respect to the first timing. The controller determines an eye of timing for the predetermined address signal by repetitively providing a predetermined command on the command and address signals, varying the first delay signal, and measuring a data signal received from the memory interface.
    Type: Application
    Filed: December 10, 2014
    Publication date: June 16, 2016
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Glenn Dearth, Anwar Kashem, Sean Cummins
  • Publication number: 20150378956
    Abstract: A plurality of registers implemented in association with a memory physical layer interface (PHY) can be used to store one or more instruction words that indicate one or more commands and one or more delays. A training engine implemented in the memory PHY can generate at-speed programmable sequences of commands for delivery to an external memory and to delay the commands based on the one or more delays. The at-speed programmable sequences of commands can be generated based on the one or more instruction words.
    Type: Application
    Filed: June 27, 2014
    Publication date: December 31, 2015
    Inventors: Glenn A. Dearth, Gerry Talbot
  • Publication number: 20150378603
    Abstract: A controller integrated in a memory physical layer interface (PHY) can be used to control training used to configure the memory PHY for communication with an associated external memory such as a dynamic random access memory (DRAM), thereby removing the need to provide training sequences over a data pipeline between a BIOS and the memory PHY. For example, a controller integrated in the memory PHY can control read training and write training of the memory PHY for communication with the external memory based on a training algorithm. The training algorithm may be a seedless training algorithm that converges on a solution for a timing delay and a voltage offset between the memory PHY and the external memory without receiving, from a basic input/output system (BIOS), seed information that characterizes a signal path traversed by training sequences or commands generated by the training algorithm.
    Type: Application
    Filed: June 27, 2014
    Publication date: December 31, 2015
    Inventors: Glenn A. Dearth, Gerry Talbot, Anwar Kashem, Edoardo Prete, Brian Amick
  • Patent number: 8760946
    Abstract: Various method and apparatus embodiments for training a delay for enabling a data strobe signal in a memory subsystem are disclosed. In one embodiment, a system includes a memory controller configured to receive a data strobe signal. The memory controller includes a training circuit. The training circuit includes a first storage circuit coupled to receive the data strobe signal on a data input and an enable signal on a clock input, and a training unit configured to, based on an output signal received from the first flip-flop, adjust a phase of the enable signal until an assertion of the enable signal coincides with a preamble indication in the data strobe signal.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: June 24, 2014
    Assignee: Advanced Micro Devices
    Inventors: Glenn A Dearth, Warren R Anderson, Anwar P Kashem, Richard W Reeves, Edoardo Prete, Gerald R Talbot
  • Publication number: 20130315014
    Abstract: Various method and apparatus embodiments for training a delay for enabling a data strobe signal in a memory subsystem are disclosed. In one embodiment, a system includes a memory controller configured to receive a data strobe signal. The memory controller includes a training circuit. The training circuit includes a first storage circuit coupled to receive the data strobe signal on a data input and an enable signal on a clock input, and a training unit configured to, based on an output signal received from the first flip-flop, adjust a phase of the enable signal until an assertion of the enable signal coincides with a preamble indication in the data strobe signal.
    Type: Application
    Filed: May 22, 2012
    Publication date: November 28, 2013
    Inventors: Glenn A Dearth, Warren R. Anderson, Anwar P. Kashem, Richard W. Reeves, Edoardo Prete, Gerald E. Talbot
  • Patent number: 8495440
    Abstract: A pseudo random bit stream generator is disclosed which has a fully programmable pseudo random polynomial up to the supported width of the CSRs, fully programmable tap selection for providing any specified combination of generator state taps, and fully programmable parallel sequence generation which determines the number of sequential bits calculated and how much the sequence generator advances per clock.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: July 23, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Glenn A. Dearth
  • Publication number: 20130055039
    Abstract: A pseudo random bit stream generator is disclosed which has a fully programmable pseudo random polynomial up to the supported width of the CSRs, fully programmable tap selection for providing any specified combination of generator state taps, and fully programmable parallel sequence generation which determines the number of sequential bits calculated and how much the sequence generator advances per clock.
    Type: Application
    Filed: August 30, 2011
    Publication date: February 28, 2013
    Inventor: Glenn A. Dearth
  • Patent number: 8260992
    Abstract: An apparatus includes a plurality of data lines defining a data bus for communicating data. A controller is operable to communicate a plurality of data transfers over the data bus using a plurality of data time slots, wherein for at least a subset of the data time slots the controller is operable to communicate an associated data bus inversion indicator indicating that bits communicated during the associated data time slot are inverted, the data bus inversion indicators for the subset of the data transfers are grouped into a data bus inversion vector, and the controller is operable to communicate a global data bus inversion indicator indicating an inversion of the data bus inversion vector.
    Type: Grant
    Filed: April 12, 2010
    Date of Patent: September 4, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Glenn A. Dearth, Shwetal A. Patel
  • Patent number: 8201179
    Abstract: A method for controlling sharing of resources in a multi-threaded environment includes entering a finite state machine state sequence; controlling resource-sharing threads using the finite state machine state sequence; and exiting the finite state machine state sequence when shared resource control is complete. A multi-threaded shared resource control system includes a finite state machine configured to control multi-threaded access to shared resources; a plurality of producer threads regulated by the finite state machine; and a plurality of consumer threads regulated by the finite state machine.
    Type: Grant
    Filed: May 4, 2006
    Date of Patent: June 12, 2012
    Assignee: Oracle America, Inc.
    Inventors: Glenn A. Dearth, Stephen A. Jay