Patents by Inventor Glenn B. Alers

Glenn B. Alers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170288080
    Abstract: A window for a greenhouse is provided that is comprised of a sheet of luminescent material [104] and light-energy converter [103]. The sheet comprises one or more luminescent materials [104] that absorb the peak wavelengths of the sun, emitting the absorbed photons to wavelengths primarily between 600 and 690 nm where they are converted to electrical power and/or enhance plant production. The luminescent material [104] is also transparent to a fraction of the wavelengths in the blue and red-portion of the solar spectrum which are required for plant growth and flowering. An additional polymer layer may be added as a luminescent layer, diffuser and/or IR reflector to further enhance plant growth and electricity generation.
    Type: Application
    Filed: June 19, 2017
    Publication date: October 5, 2017
    Inventors: Sue A. Carter, Glenn B. Alers, Michael E. Loik
  • Publication number: 20140352762
    Abstract: A window for a greenhouse is provided that is comprised of a sheet of luminescent material [104] and light-energy converter [103]. The sheet comprises one or more luminescent materials [104] that absorb the peak wavelengths of the sun, emitting the absorbed photons to wavelengths primarily between 600 and 690 nm where they are converted to electrical power and/or enhance plant production. The luminescent material [104] is also transparent to a fraction of the wavelengths in the blue and red-portion of the solar spectrum which are required for plant growth and flowering. An additional polymer layer may be added as a luminescent layer, diffuser and/or IR reflector to further enhance plant growth and electricity generation.
    Type: Application
    Filed: February 1, 2013
    Publication date: December 4, 2014
    Inventors: Sue A. Carter, Glenn B. Alers, Michael E. Loik
  • Patent number: 8030777
    Abstract: Methods of protecting exposed metal damascene interconnect surfaces in a process for making electronic components and the electronic components made according to such methods. An integrated circuit structure having damascene regions with exposed metal surfaces is provided into a closed processing chamber, whereby a first reactant is contacted to the exposed metal surfaces to transform a top portion of the metal layer into a protective self-aligned buffer layer. Reacting molecules of the first reactant with metal atoms of this metal layer forms the protective self-aligned buffer layer entirely within such metal layer. Alternatively, adsorbing surface-active reactant molecules onto the exposed metal surface forms the protective self-aligned buffer layer. A second reactant may be contacted to the protective self-aligned buffer layer to form a self-aligned dielectric cap layer directly over the protective self-aligned buffer layer.
    Type: Grant
    Filed: February 5, 2007
    Date of Patent: October 4, 2011
    Assignee: Novellus Systems, Inc.
    Inventors: Bart van Schravendijk, Thomas W Mountsier, Mahesh K Sanganeria, Glenn B Alers, Roey Shaviv
  • Patent number: 7396759
    Abstract: Methods of protecting exposed metal damascene interconnect surfaces in a process for making electronic components and the electronic components made according to such methods. An integrated circuit structure having damascene regions with exposed metal surfaces is provided into a closed processing chamber, whereby a first reactant is contacted to the exposed metal surfaces to transform a top portion of the metal layer into a protective self-aligned buffer layer. Reacting molecules of the first reactant with metal atoms of this metal layer forms the protective self-aligned buffer layer entirely within such metal layer. Alternatively, adsorbing surface-active reactant molecules onto the exposed metal surface forms the protective self-aligned buffer layer. A second reactant may be contacted to the protective self-aligned buffer layer to form a self-aligned dielectric cap layer directly over the protective self-aligned buffer layer.
    Type: Grant
    Filed: November 3, 2004
    Date of Patent: July 8, 2008
    Assignee: Novellus Systems, Inc.
    Inventors: Bart van Schravendijk, Thomas W Mountsier, Mahesh K Sanganeria, Glenn B Alers, Roey Shaviv
  • Patent number: 6830942
    Abstract: A method is disclosed for processing a silicon workpiece including a hybrid thermometer system for measuring and controlling the processing temperature where fabrication materials have been or are being applied to the workpiece. The hybrid thermometer system uses optical reflectance and another thermometer technique, such as a thermocouple and/or a pyrometer. Real-time spectral data are compared to values in a spectrum library to determine the “surface conditions”. A decision is then made based on the surface conditions as to how the temperature is measured, e.g., with optical reflectance, a pyrometer, or a thermocouple, and the temperature is measured using the appropriately selected technique. Utilizing the hybrid thermometer system, the temperature of a silicon workpiece may be accurately measured at low temperatures while accounting for the presence of fabrication materials.
    Type: Grant
    Filed: April 6, 1999
    Date of Patent: December 14, 2004
    Assignee: Lucent Technologies Inc.
    Inventors: Glenn B. Alers, Robert J. Chichester, Don X. Sun, Gordon Albert Thomas
  • Patent number: 6750495
    Abstract: A capacitor structure is formed in a window in a dielectric layer of an integrated circuit. The lower electrode (or plate) is disposed on a portion side surface of the cavity but not on the top surface of the dielectric. A layer of dielectric material is disposed on the lower electrode and upon the top surface of the integrated circuit dielectric. Finally, an upper electrode (or plate) is disposed on the layer of dielectric material. Because the lower electrode is removed from a portion of the cavity sidewall and top surface of the dielectric shorting problems which could result during planarization are avoided. A technique for fabricating an integrated circuit (IC) for use in multi-level structures is also disclosed. The technique is readily incorporated into standard multi-level processing techniques. After a window is opened in the particular dielectric layer of the IC, a conductive layer is deposited in the window and forms the lower plate of a capacitor.
    Type: Grant
    Filed: May 12, 1999
    Date of Patent: June 15, 2004
    Assignee: Agere Systems Inc.
    Inventors: Glenn B. Alers, Tseng-Chung Lee, Helen Louise Maynard, Daniel Joseph Vitkavage
  • Patent number: 6559499
    Abstract: A process for fabricating trench capacitors in an interconnect layer of a semiconductor device is disclosed. In the process, at least one interconnect is formed in the interconnect layer, which is then planarized. To form the trench capacitor, a trench is formed in the dielectric material of the interconnect. The bottom of the trench communicates with a metal contact in the underlying layer. A barrier layer of material is formed on the interconnect layer and is anisotropically etched, leaving the barrier layer on the sidewalls of the trench. The lower plate of the capacitor is then formed by depositing a layer of metal over the interconnect layer. The layer of metal is then anisotropically etched, removing the metal on the surface of the interconnect layer and leaving the metal along the trench perimeter. The capacitor dielectric layer is then deposited over the interconnect layer and subsequently patterned. Another layer of barrier material is deposited on the interconnect layer.
    Type: Grant
    Filed: January 4, 2000
    Date of Patent: May 6, 2003
    Assignee: Agere Systems Inc.
    Inventors: Glenn B Alers, Philip W Diodato, Ruichen Liu
  • Patent number: 6403415
    Abstract: The present invention provides a semiconductor device that has a metal barrier layer for a dielectric material, which can be used in an integrated circuit, if so desired. The semiconductor device provides a capacitance to the integrated circuit and in a preferred embodiment comprises a first layer located on a surface of the integrated circuit. A metal barrier layer is located on the first layer and is susceptible to oxidation by oxygen. A high K capacitor dielectric layer (i.e., a higher K than silicon dioxide) that contains oxygen, such as tantalum pentoxide, is located over the metal barrier layer. The semiconductor device further includes a first layer located over the high K capacitor dielectric layer.
    Type: Grant
    Filed: January 11, 2000
    Date of Patent: June 11, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Glenn B. Alers, Sailesh M. Merchant, Pradip K. Roy
  • Patent number: 6320479
    Abstract: In accordance with the invention, magnetostrictive saw devices are provided with improved transducer structures for enhanced performance. In one improved device, the transducers are in the form of gratings with interconnected ends for reduced resistance and inductance. In another embodiment, the transducers are shaped to provide apodization. In yet a third embodiment, transducer performance is enhanced by patterning composite structures.
    Type: Grant
    Filed: December 17, 1999
    Date of Patent: November 20, 2001
    Assignee: Agere Systems Optoelectronics Guardian Corp.
    Inventors: Glenn B. Alers, Kenneth Alexander Ellis, Timothy J. Klemmer, Robert Bruce Van Dover
  • Patent number: 6320244
    Abstract: An integrated circuit device includes a dielectric layer having an opening therein, and a capacitor comprising in stacked relation a lower electrode lining the opening, a capacitor dielectric layer adjacent the lower electrode, and an upper electrode adjacent the capacitor dielectric layer. The capacitor has a substantially planar upper surface substantially flush with adjacent upper surface portions of the dielectric layer. Additionally, the edges of the lower electrode and the capacitor dielectric layer preferably terminate at the upper surface of the capacitor. Also, the capacitor dielectric may include a high-k, high quality and low leakage dielectric, and which prevents the reduction of the capacitor dielectric by the metal of the upper and lower metal electrodes.
    Type: Grant
    Filed: September 2, 1999
    Date of Patent: November 20, 2001
    Assignee: Agere Systems Guardian Corp.
    Inventors: Glenn B. Alers, Seungmoo Choi, Sailesh Mansinh Merchant, Pradip Kumar Roy
  • Patent number: 6303426
    Abstract: A method of forming a capacitor having a tungsten bottom electrode in a semiconductor wafer that eliminates the effects of oxidation of the surface of the bottom electrode on capacitor performance.
    Type: Grant
    Filed: January 6, 2000
    Date of Patent: October 16, 2001
    Assignee: Agere Systems Guardian Corp.
    Inventor: Glenn B. Alers
  • Patent number: 6284663
    Abstract: An electronic device having an improved capacitor structure is formed by depositing a metal layer defining a first electrode on a film of high dielectric constant material, and then depositing the dielectric layer of the capacitor structure on the first electrode. This resulting structure is then exposed to a nitrogen plasma and the top electrode is formed. Exposing the first electrode to a plasma of pure nitrogen prevents the partial oxidation of the first electrode and reduces the density of charge traps at the electrode/dielectric interface. The dielectric film is passivated with the nitrogen material before forming the top electrode to prevent interdiffusion between the electrode and the dielectric.
    Type: Grant
    Filed: November 4, 1999
    Date of Patent: September 4, 2001
    Assignee: Agere Systems Guardian Corp.
    Inventor: Glenn B. Alers
  • Patent number: 6271596
    Abstract: The present invention relates to a conductive plug capacitor and method of making for use in multi-level integrated circuit structures. In one embodiment, a tungsten plug is formed in a window in a dielectric layer and thereafter a cavity is formed in the plug. This cavity in the plug may serve as the lower electrode for the capacitor, with a layer of dielectric deposited in the cavity and a top metal electrode deposited on the dielectric layer. An alternative embodiment makes use of not only the inner cavity surfaces of the cavity in the tungsten plug, but also the outer sidewalls of the tungsten plug. To this end, after formation of the tungsten plug heading the cavity formed therein, a partial etchback of the dielectric layer in which the tungsten plug is formed is effective. The capacitor dielectric is then deposited on the sidewalls, the top surface and the interior of the cavity of the tungsten plug thereby increasing the area and thereby the over capacitance.
    Type: Grant
    Filed: April 15, 1999
    Date of Patent: August 7, 2001
    Assignee: Agere Systems Guardian Corp.
    Inventor: Glenn B. Alers
  • Patent number: 6265260
    Abstract: A method for making an integrated circuit capacitor which in one embodiment preferably comprises the steps of: forming, adjacent a semiconductor substrate, a first metal electrode comprising a metal nitride surface portion; forming a tantalum pentoxide layer on the metal nitride surface portion while maintaining a temperature below an oxidizing temperature of the metal; remote plasma annealing the tantalum pentoxide layer; and forming a second electrode adjacent the tantalum pentoxide layer. The step of forming the tantalum pentoxide layer preferably comprises chemical vapor deposition of the tantalum pentoxide at a temperature below about 500° C. Accordingly, oxidation of the metal is avoided and a high quality tantalum pentoxide is produced. The metal of the first metal electrode may comprise at least one of titanium, tungsten, tantalum, and alloys thereof.
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: July 24, 2001
    Assignee: Lucent Technologies Inc.
    Inventors: Glenn B. Alers, Pradip Kumar Roy
  • Patent number: 6046657
    Abstract: An improved surface acoustic wave device includes a film of a magnetostrictive material disposed on a substrate and spaced apart input and output transducer elements disposed on the film. The input element causes horizontally polarized shear waves to propagate along the film via the magnetostriction of the film. The shear waves propagating along the film are received by the output transducer element. The SAW device can be integrated on a microelectronic circuit useable in single chip radio frequency applications.
    Type: Grant
    Filed: August 21, 1998
    Date of Patent: April 4, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Glenn B. Alers, Robert Bruce Van Dover
  • Patent number: 6001741
    Abstract: An electronic device is formed by depositing a thin film of high dielectric constant material on a silicon substrate, exposing the structure to plasma, and then forming the top electrode. The plasma substantially reduces the density of charge traps at the dielectric/silicon interface. Advantageously, the dielectric film is passivated with a nitrogen-containing material before forming the top electrode to prevent interdiffusion between the electrode and the dielectric.
    Type: Grant
    Filed: April 15, 1998
    Date of Patent: December 14, 1999
    Assignee: Lucent Technologies Inc.
    Inventor: Glenn B. Alers
  • Patent number: 6002113
    Abstract: Apparatus for processing a silicon workpiece uses reflected UV light to measure and control the workpiece temperature. A linearly polarized beam including UV light is directed onto a silicon surface to produce a reflected beam. The reflected beam is cross-polarized to null out much of the light, and the resulting residual reflectivity spectrum is determined. The temperature is determined from the characteristics of this spectrum. A workpiece heating station uses this measuring technique to accurately control the temperature of a silicon workpiece and temperature-dependent processing over a wide range of processing temperatures, including temperatures below 500.degree. C.
    Type: Grant
    Filed: May 18, 1998
    Date of Patent: December 14, 1999
    Assignee: Lucent Technologies Inc.
    Inventors: Glenn B. Alers, Robert M. Fleming, Barry Franklin Levine, Gordon Albert Thomas