Patents by Inventor Glenn B. Graham

Glenn B. Graham has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Alternative hierarchical views of a circuit design
    Patent number: 10248751
    Abstract: Methods and apparatuses are described for creating, editing, and viewing a floorplan of a circuit design. Specifically, some embodiments enable a user to perform a graphical operation at an inference point in a circuit design layout, wherein the location of the inference point is determined based on existing graphical objects in the circuit design layout. Some embodiments substantially instantaneously update a congestion indicator in a circuit design layout in response to modifying the circuit design layout. Some embodiments substantially instantaneously update pin locations of a block or partition in response to changing the size or shape of the block or partition. Some embodiments enable a user to view a circuit design layout based on the logical hierarchy, and also based on at least one additional attribute type such as voltage, power, or clock domain.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: April 2, 2019
    Assignee: Synopsys, Inc.
    Inventors: Glenn B. Graham, Ajay Guleria, Jeffrey J. Loescher
  • ALTERNATIVE HIERARCHICAL VIEWS OF A CIRCUIT DESIGN
    Publication number: 20170091367
    Abstract: Methods and apparatuses are described for creating, editing, and viewing a floorplan of a circuit design. Specifically, some embodiments enable a user to perform a graphical operation at an inference point in a circuit design layout, wherein the location of the inference point is determined based on existing graphical objects in the circuit design layout. Some embodiments substantially instantaneously update a congestion indicator in a circuit design layout in response to modifying the circuit design layout. Some embodiments substantially instantaneously update pin locations of a block or partition in response to changing the size or shape of the block or partition. Some embodiments enable a user to view a circuit design layout based on the logical hierarchy, and also based on at least one additional attribute type such as voltage, power, or clock domain.
    Type: Application
    Filed: December 8, 2016
    Publication date: March 30, 2017
    Applicant: Synopsys, Inc.
    Inventors: Glenn B. Graham, Ajay Guleria, Jeffrey J. Loescher