Abstract: A memory including an array of memory cells, word lines, and voltage supply lines. Each voltage supply line of the plurality of voltage supply lines is coupled to a first voltage supply terminal of a subset of memory cells of subsets of memory cells of the array. Each memory cell of the array is coupled to a word line. The memory includes a row decoder that controls a voltage on each of the word lines and controls a voltage on each of the voltage supply lines. The row decoder provides a low voltage state voltage on one of the voltage supply lines during a write operation to a subset of memory cells coupled to the voltage supply line and the row decoder provides a high voltage state voltage to the voltage supply line during a read operation of the subset of the memory cells.

Abstract: A memory including an array of memory cells, word lines, and voltage supply lines. Each voltage supply line of the plurality of voltage supply lines is coupled to a first voltage supply terminal of a subset of memory cells of subsets of memory cells of the array. Each memory cell of the array is coupled to a word line. The memory includes a row decoder that controls a voltage on each of the word lines and controls a voltage on each of the voltage supply lines. The row decoder provides a low voltage state voltage on one of the voltage supply lines during a write operation to a subset of memory cells coupled to the voltage supply line and the row decoder provides a high voltage state voltage to the voltage supply line during a read operation of the subset of the memory cells.

Abstract: A method of making a semiconductor device is achieved in and over a semiconductor layer. A trench is formed adjacent to a first active area. The trench is filled with insulating material. A masking feature is formed over a center portion of the trench to expose a first side of the trench between a first side of the masking feature and the first active area. A step of etching into the first side of the trench leaves a first recess in the trench. A first epitaxial region is grown in the first recess to extend the first active area to include the first recess and thereby form an extended first active region.

Abstract: A method of making a semiconductor device is achieved in and over a semiconductor layer. A trench is formed adjacent to a first active area. The trench is filled with insulating material. A masking feature is formed over a center portion of the trench to expose a first side of the trench between a first side of the masking feature and the first active area. A step of etching into the first side of the trench leaves a first recess in the trench. A first epitaxial region is grown in the first recess to extend the first active area to include the first recess and thereby form an extended first active region.

Abstract: A semiconductor device is formed on a semiconductor layer. A gate dielectric layer is formed over the semiconductor layer. A layer of gate material is formed over the gate dielectric layer. The layer of gate material is patterned to form a gate structure. Using the gate structure as a mask, an implant into the semiconductor layer is performed. To form a first patterned gate structure and a trench in the semiconductor layer surrounding a first portion and a second portion of the semiconductor layer and the gate, an etch through the gate structure and the semiconductor layer is performed. The trench is filled with insulating material.

Abstract: A method of making a semiconductor device is achieved in and over a semiconductor layer. A trench is formed adjacent to a first active area. The trench is filled with insulating material. A masking feature is formed over a center portion of the trench to expose a first side of the trench between a first side of the masking feature and the first active area. A step of etching into the first side of the trench leaves a first recess in the trench. A first epitaxial region is grown in the first recess to extend the first active area to include the first recess and thereby form an extended first active region.

Abstract: A memory cell including an access transistor coupled to a first storage node and a read port coupled to one of the first storage node or a second storage node is provided. The memory cell further includes a first inverter having an input terminal coupled to the first storage node, an output terminal, and a first power supply voltage terminal for receiving a first power supply voltage. The memory cell further includes a second inverter having an input terminal coupled to the output terminal of the first inverter, an output terminal coupled to the input terminal of the first inverter at the first storage node, and a second power supply voltage terminal for receiving a second power supply voltage, wherein the second power supply voltage is varied relative to the first power supply voltage during a write operation to the memory cell.

Abstract: A two-port SRAM memory cell includes a pair of cross-coupled inverters coupled to storage nodes. An access transistor is coupled between each storage node and a write bit line and controlled by a write word line. The write word line is also coupled to a power supply terminal of the pair of cross-coupled inverters. During a write operation, the write word line is asserted. A voltage at the power supply terminal of the cross-coupled inverters follows the write word line voltage, thus making it easier for the stored logic state at the storage nodes to change, if necessary. At the end of the write operation, the write word line is de-asserted, allowing the cross-coupled inverters to function normally and hold the logic state of the storage node. Coupling the power supply node of the cross-coupled inverters allows faster write operations without harming cell stability.

Abstract: A semiconductor device is formed on a semiconductor layer. A gate dielectric layer is formed over the semiconductor layer. A layer of gate material is formed over the gate dielectric layer. The layer of gate material is patterned to form a gate structure. Using the gate structure as a mask, an implant into the semiconductor layer is performed. To form a first patterned gate structure and a trench in the semiconductor layer surrounding a first portion and a second portion of the semiconductor layer and the gate, an etch through the gate structure and the semiconductor layer is performed. The trench is filled with insulating material.

Abstract: A memory cell including an access transistor coupled to a first storage node and a read port coupled to one of the first storage node or a second storage node is provided. The memory cell further includes a first inverter having an input terminal coupled to the first storage node, an output terminal, and a first power supply voltage terminal for receiving a first power supply voltage. The memory cell further includes a second inverter having an input terminal coupled to the output terminal of the first inverter, an output terminal coupled to the input terminal of the first inverter at the first storage node, and a second power supply voltage terminal for receiving a second power supply voltage, wherein the second power supply voltage is varied relative to the first power supply voltage during a write operation to the memory cell.

Abstract: A two-port SRAM memory cell includes a pair of cross-coupled inverters coupled to storage nodes. An access transistor is coupled between each storage node and a write bit line and controlled by a write word line. The write word line is also coupled to a power supply terminal of the pair of cross-coupled inverters. During a write operation, the write word line is asserted. A voltage at the power supply terminal of the cross-coupled inverters follows the write word line voltage, thus making it easier for the stored logic state at the storage nodes to change, if necessary. At the end of the write operation, the write word line is de-asserted, allowing the cross-coupled inverters to function normally and hold the logic state of the storage node. Coupling the power supply node of the cross-coupled inverters allows faster write operations without harming cell stability.

Abstract: A method for making an integrated circuit includes the steps of forming a plurality of spaced apart isolation regions in a substrate to define active regions therebetween, forming a first mask, and using the first mask for performing at least one implant in the active regions for defining high voltage active regions for the high voltage transistors. The method further includes the steps of removing the first mask and forming a second mask, and using the second mask for performing only one implant for converting at least one high voltage active region into a low voltage active region for a low voltage transistor. All of the implants needed to define the high voltage transistors are first performed throughout the active regions using the first mask. A separate single implant is then performed using the second mask to convert at least one of the high voltage active regions to a low voltage active region.