Abstract: A method for operating a Reduced Instruction Set Computer (RISC) processor that executes normal RISC instructions and special RISC instructions. The method comprises the step of controlling the RISC processor to perform a single operation, using a single functional unit of the RISC processor, in response to each normal RISC instruction. The method also comprises the step of controlling the RISC processor to perform multiple operations, using multiple functional units of the RISC processor in parallel, in response to each special RISC instruction.

Abstract: A method for operating a Reduced Instruction Set Computer (RISC) processor that executes mormal RISC instructions and special RISC instructions. The method comprises the step of controlling the RISC processor to perform a single operation, using a single functional unit for each RISC processor, in response to each normal RISC instruction. The method also comprises the step of controlling the RISC processor to perform multiple operations, using multiple functional units of the RISC processor in parallel, in response to each special RISC instruction.

Abstract: A circuit in a graphics processing subsystem receives pixel color values as input and concurrently provides both dithering and scale correction of the color values. Pixel color values are initially generated by the subsystem as 8-bit binary quantities, each having a maximum possible value of 255. However, the graphics processing subsystem utilizes a scale of 0 to 256 for processing color values. The correction function prevents a loss of pixel intensity that would otherwise result from representing 8-bit color values on a 0 to 256 scale.

Abstract: A method and apparatus for performing color space conversion using blend circuitry in a graphics/video adapter is provided. Blend circuitry which is capable of blending two color values and fog circuitry which is capable of adjusting color values based on a fog factor are used. A first stage of converting a color value from YC.sub.r C.sub.b (YUV) color space to RGB color space is performed using the fog circuitry, and a second stage of converting the color value from the YC.sub.r C.sub.b (YUV) color space to RGB color space is performed using the blend circuitry, resulting in the generation of a converted color value .

Abstract: A pixel engine pipeline (including a "front-end" and a "back-end") communicates pixel information between a graphics processor, a pixel engine, a data cache, and system memory. The "front-end" (for reading requested data) includes a command queue for receiving graphics instructions from a graphics processor. Read requests in the command queue are stored in a read request queue. Extraction instructions corresponding to at least a portion of the read request are stored in an attribute queue. Control logic determines whether the requested data is located in a data cache. The read request is stored in a load request queue and the requested data is retrieved from system memory into a load data queue, if the requested data is not in the data cache. The control logic stores the requested data into a read data queue. The requested data is provided to a stage of the pixel engine from the read data queue in accordance with the extraction instructions.

Abstract: A method for operating a Reduced Instruction Set Computer (RISC) processor that executes normal RISC instructions and special RISC instructions. The method comprises the step of controlling the RISC processor to perform a single operation, using a single functional unit of the RISC processor, in response to each normal RISC instruction. The method also comprises the step of controlling the RISC processor to perform multiple operations, using multiple functional units of the RISC processor in parallel, in response to each special RISC instruction.

Abstract: System and method for the rasterization of polygons. Each edge of the polygon (e.g., a triangle) is represented by a linear edge function which classifies each pixel within the plane of the polygon. In particular, pixels having a value greater than zero are on one side of an edge and less than zero on the opposite side of an edge. Each pixel within the plane of the polygon has associated with it a set of edge variables which represent the signed, horizontal distance between the pixel and the respective edges of the polygon. A pixel is rendered based on the value of a pixels edge variables which is generated with reference to the edge functions. The edge functions are applied to a linear span of pixels. Initially, the value of a set of edge variables for a given pixel within a triangle is determined by evaluating the three edge functions associated with that triangle. In order to determine which pixels to render, the present invention generates a W-bit render mask based upon the values of these edge variables.

Abstract: A context switching system for saving, restoring or swapping tasks, and is adapted for use in a multitasking processor coupled to an external or system memory. The processor includes one or more functional blocks to perform the tasks. The functional blocks comprise registers that store state data that, at a particular instant, represents the context of the system. The system comprises a controller that receives a save or switch command and generates a context save instruction in response thereto. The controller is configured to pass the context save instruction to the functional blocks. The functional blocks generate a state program. The state program comprises one or more register load instructions and the state data representing the context of the system so that context can be restored at a later time. The state program is stored in an external or system memory. Saving context as state programs permits the system to quickly switch from one context to another without losing important information.