Abstract: A circuit samples and stores high frequency transient events that affect low frequency steady state signals. The circuit digitizes the high frequency transient signal and samples the digital signals. The present and previously stored data samples are compared, and if the difference exceeds a threshold, the present sample is stored in memory, if the memory is not full, and simultaneously the internal counter is reset. If a number of successive samples do not exceed the threshold and are not stored within a defined interval, the last sample of the interval is stored and an interval counter is reset to zero. A logic circuit controls the timing and operation of the counter and storage of the sampled data.